X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fmach-imx%2Fcpu.c;h=f2070c97143261541ea8e3382467b48e66d8c949;hb=c27178ba3649f539c9f1890ea147f4c5415f63b5;hp=93e60b2039ad4aeb6cd70bc9ea4b74662f9d9d2a;hpb=42dc1230cdec48d0278dcc683bc14527cbea12c5;p=oweals%2Fu-boot.git diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c index 93e60b2039..f2070c9714 100644 --- a/arch/arm/mach-imx/cpu.c +++ b/arch/arm/mach-imx/cpu.c @@ -8,6 +8,9 @@ #include #include +#include +#include +#include #include #include #include @@ -21,8 +24,8 @@ #include #include -#ifdef CONFIG_FSL_ESDHC -#include +#ifdef CONFIG_FSL_ESDHC_IMX +#include #endif static u32 reset_cause = -1; @@ -87,66 +90,43 @@ static char *get_reset_cause(void) } #endif -#if defined(CONFIG_MX53) || defined(CONFIG_MX6) -#if defined(CONFIG_MX53) -#define MEMCTL_BASE ESDCTL_BASE_ADDR -#else -#define MEMCTL_BASE MMDC_P0_BASE_ADDR -#endif -static const unsigned char col_lookup[] = {9, 10, 11, 8, 12, 9, 9, 9}; -static const unsigned char bank_lookup[] = {3, 2}; - -/* these MMDC registers are common to the IMX53 and IMX6 */ -struct esd_mmdc_regs { - uint32_t ctl; - uint32_t pdc; - uint32_t otc; - uint32_t cfg0; - uint32_t cfg1; - uint32_t cfg2; - uint32_t misc; -}; - -#define ESD_MMDC_CTL_GET_ROW(mdctl) ((ctl >> 24) & 7) -#define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((ctl >> 20) & 7) -#define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((ctl >> 16) & 3) -#define ESD_MMDC_CTL_GET_CS1(mdctl) ((ctl >> 30) & 1) -#define ESD_MMDC_MISC_GET_BANK(mdmisc) ((misc >> 5) & 1) - -/* - * imx_ddr_size - return size in bytes of DRAM according MMDC config - * The MMDC MDCTL register holds the number of bits for row, col, and data - * width and the MMDC MDMISC register holds the number of banks. Combine - * all these bits to determine the meme size the MMDC has been configured for - */ -unsigned imx_ddr_size(void) -{ - struct esd_mmdc_regs *mem = (struct esd_mmdc_regs *)MEMCTL_BASE; - unsigned ctl = readl(&mem->ctl); - unsigned misc = readl(&mem->misc); - int bits = 11 + 0 + 0 + 1; /* row + col + bank + width */ - - bits += ESD_MMDC_CTL_GET_ROW(ctl); - bits += col_lookup[ESD_MMDC_CTL_GET_COLUMN(ctl)]; - bits += bank_lookup[ESD_MMDC_MISC_GET_BANK(misc)]; - bits += ESD_MMDC_CTL_GET_WIDTH(ctl); - bits += ESD_MMDC_CTL_GET_CS1(ctl); - - /* The MX6 can do only 3840 MiB of DRAM */ - if (bits == 32) - return 0xf0000000; - - return 1 << bits; -} -#endif - #if defined(CONFIG_DISPLAY_CPUINFO) && !defined(CONFIG_SPL_BUILD) const char *get_imx_type(u32 imxtype) { switch (imxtype) { + case MXC_CPU_IMX8MP: + return "8MP"; /* Quad-core version of the imx8mp */ + case MXC_CPU_IMX8MN: + return "8MNano Quad"; /* Quad-core version */ + case MXC_CPU_IMX8MND: + return "8MNano Dual"; /* Dual-core version */ + case MXC_CPU_IMX8MNS: + return "8MNano Solo"; /* Single-core version */ + case MXC_CPU_IMX8MNL: + return "8MNano QuadLite"; /* Quad-core Lite version */ + case MXC_CPU_IMX8MNDL: + return "8MNano DualLite"; /* Dual-core Lite version */ + case MXC_CPU_IMX8MNSL: + return "8MNano SoloLite"; /* Single-core Lite version */ + case MXC_CPU_IMX8MM: + return "8MMQ"; /* Quad-core version of the imx8mm */ + case MXC_CPU_IMX8MML: + return "8MMQL"; /* Quad-core Lite version of the imx8mm */ + case MXC_CPU_IMX8MMD: + return "8MMD"; /* Dual-core version of the imx8mm */ + case MXC_CPU_IMX8MMDL: + return "8MMDL"; /* Dual-core Lite version of the imx8mm */ + case MXC_CPU_IMX8MMS: + return "8MMS"; /* Single-core version of the imx8mm */ + case MXC_CPU_IMX8MMSL: + return "8MMSL"; /* Single-core Lite version of the imx8mm */ case MXC_CPU_IMX8MQ: - return "8MQ"; /* Quad-core version of the imx8m */ + return "8MQ"; /* Quad-core version of the imx8mq */ + case MXC_CPU_IMX8MQL: + return "8MQLite"; /* Quad-core Lite version of the imx8mq */ + case MXC_CPU_IMX8MD: + return "8MD"; /* Dual-core version of the imx8mq */ case MXC_CPU_MX7S: return "7S"; /* Single-core version of the mx7 */ case MXC_CPU_MX7D: @@ -173,6 +153,8 @@ const char *get_imx_type(u32 imxtype) return "6UL"; /* Ultra-Lite version of the mx6 */ case MXC_CPU_MX6ULL: return "6ULL"; /* ULL version of the mx6 */ + case MXC_CPU_MX6ULZ: + return "6ULZ"; /* ULZ version of the mx6 */ case MXC_CPU_MX51: return "51"; case MXC_CPU_MX53: @@ -189,12 +171,12 @@ int print_cpuinfo(void) cpurev = get_cpu_rev(); -#if defined(CONFIG_IMX_THERMAL) +#if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU) struct udevice *thermal_dev; int cpu_tmp, minc, maxc, ret; printf("CPU: Freescale i.MX%s rev%d.%d", - get_imx_type((cpurev & 0xFF000) >> 12), + get_imx_type((cpurev & 0x1FF000) >> 12), (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0); max_freq = get_cpu_speed_grade_hz(); @@ -206,13 +188,13 @@ int print_cpuinfo(void) } #else printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", - get_imx_type((cpurev & 0xFF000) >> 12), + get_imx_type((cpurev & 0x1FF000) >> 12), (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, mxc_get_clock(MXC_ARM_CLK) / 1000000); #endif -#if defined(CONFIG_IMX_THERMAL) +#if defined(CONFIG_IMX_THERMAL) || defined(CONFIG_IMX_TMU) puts("CPU: "); switch (get_cpu_temp_grade(&minc, &maxc)) { case TEMP_AUTOMOTIVE: @@ -258,7 +240,7 @@ int cpu_eth_init(bd_t *bis) return rc; } -#ifdef CONFIG_FSL_ESDHC +#ifdef CONFIG_FSL_ESDHC_IMX /* * Initializes on-chip MMC controllers. * to override, implement board_mmc_init() @@ -289,16 +271,18 @@ void arch_preboot_os(void) imx_pcie_remove(); #endif #if defined(CONFIG_SATA) - sata_remove(0); + if (!is_mx6sdl()) { + sata_remove(0); #if defined(CONFIG_MX6) - disable_sata_clock(); + disable_sata_clock(); #endif + } #endif #if defined(CONFIG_VIDEO_IPUV3) /* disable video before launching O/S */ ipuv3_fb_shutdown(); #endif -#if defined(CONFIG_VIDEO_MXS) +#if defined(CONFIG_VIDEO_MXS) && !defined(CONFIG_DM_VIDEO) lcdif_power_down(); #endif } @@ -347,6 +331,7 @@ enum cpu_speed { OCOTP_TESTER3_SPEED_GRADE1, OCOTP_TESTER3_SPEED_GRADE2, OCOTP_TESTER3_SPEED_GRADE3, + OCOTP_TESTER3_SPEED_GRADE4, }; u32 get_cpu_speed_grade_hz(void) @@ -359,17 +344,28 @@ u32 get_cpu_speed_grade_hz(void) val = readl(&fuse->tester3); val >>= OCOTP_TESTER3_SPEED_SHIFT; - val &= 0x3; + + if (is_imx8mn() || is_imx8mp()) { + val &= 0xf; + return 2300000000 - val * 100000000; + } + + if (is_imx8mm()) + val &= 0x7; + else + val &= 0x3; switch(val) { case OCOTP_TESTER3_SPEED_GRADE0: return 800000000; case OCOTP_TESTER3_SPEED_GRADE1: - return is_mx7() ? 500000000 : 1000000000; + return (is_mx7() ? 500000000 : (is_imx8mq() ? 1000000000 : 1200000000)); case OCOTP_TESTER3_SPEED_GRADE2: - return is_mx7() ? 1000000000 : 1300000000; + return (is_mx7() ? 1000000000 : (is_imx8mq() ? 1300000000 : 1600000000)); case OCOTP_TESTER3_SPEED_GRADE3: - return is_mx7() ? 1200000000 : 1500000000; + return (is_mx7() ? 1200000000 : (is_imx8mq() ? 1500000000 : 1800000000)); + case OCOTP_TESTER3_SPEED_GRADE4: + return 2000000000; } return 0; @@ -412,7 +408,7 @@ u32 get_cpu_temp_grade(int *minc, int *maxc) } #endif -#if defined(CONFIG_MX7) || defined(CONFIG_IMX8M) +#if defined(CONFIG_MX7) || defined(CONFIG_IMX8MQ) || defined(CONFIG_IMX8MM) enum boot_device get_boot_device(void) { struct bootrom_sw_info **p =