X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fmach-exynos%2Fdmc_init_ddr3.c;h=6a5d26cc69dbe7952c1a98416b9a4315a56c3451;hb=0ae7050c25a1ccfec7c7b0ebf0751997eaa7029b;hp=25a9df936479c8ce18a01e5b676e81ea096294e2;hpb=60b25259a5540686add02cf6c94cd7494a3e2d23;p=oweals%2Fu-boot.git

diff --git a/arch/arm/mach-exynos/dmc_init_ddr3.c b/arch/arm/mach-exynos/dmc_init_ddr3.c
index 25a9df9364..6a5d26cc69 100644
--- a/arch/arm/mach-exynos/dmc_init_ddr3.c
+++ b/arch/arm/mach-exynos/dmc_init_ddr3.c
@@ -618,7 +618,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
 		/*
 		 * Send NOP, MRS and ZQINIT commands
 		 * Sending MRS command will reset the DRAM. We should not be
-		 * reseting the DRAM after resume, this will lead to memory
+		 * resetting the DRAM after resume, this will lead to memory
 		 * corruption as DRAM content is lost after DRAM reset
 		 */
 		dmc_config_mrs(mem, &drex0->directcmd);