X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fmach-at91%2Finclude%2Fmach%2Fsama5d4.h;h=e2edb6a51b119959f84cc86a1da309111a327937;hb=83d290c56fab2d38cd1ab4c4cc7099559c1d5046;hp=f30cb5fed1d0a03acbdfa65334136c26a103bf7b;hpb=e1cc4d31f889428a4ca73120951389c756404184;p=oweals%2Fu-boot.git

diff --git a/arch/arm/mach-at91/include/mach/sama5d4.h b/arch/arm/mach-at91/include/mach/sama5d4.h
index f30cb5fed1..e2edb6a51b 100644
--- a/arch/arm/mach-at91/include/mach/sama5d4.h
+++ b/arch/arm/mach-at91/include/mach/sama5d4.h
@@ -1,20 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Chip-specific header file for the SAMA5D4 SoC
  *
  * Copyright (C) 2014 Atmel
  *		      Bo Shen <voice.shen@atmel.com>
- *
- * SPDX-License-Identifier:     GPL-2.0+
  */
 
 #ifndef __SAMA5D4_H
 #define __SAMA5D4_H
 
-/*
- * defines to be used in other places
- */
-#define CONFIG_AT91FAMILY	/* It's a member of AT91 */
-
 /*
  * Peripheral identifiers/interrupts.
  */
@@ -144,6 +138,9 @@
 #define ATMEL_BASE_PIOE		0xfc06d000
 #define ATMEL_BASE_AIC		0xfc06e000
 
+#define ATMEL_CHIPID_CIDR	0xfc069040
+#define ATMEL_CHIPID_EXID	0xfc069044
+
 /*
  * Internal Memory.
  */
@@ -171,11 +168,37 @@
  * Other misc defines
  */
 #define ATMEL_PIO_PORTS		5
-#define CPU_HAS_PIO3
-#define PIO_SCDR_DIV		0x3fff
 #define CPU_HAS_PCR
 #define CPU_HAS_H32MXDIV
 
+/* MATRIX0(H64MX) slave id definitions */
+#define H64MX_SLAVE_AXIMX_BRIDGE	0	/* Bridge from H64MX to AXIMX */
+#define H64MX_SLAVE_PERIPH_BRIDGE	1	/* H64MX Peripheral Bridge */
+#define H64MX_SLAVE_VDEC		2	/* Video Decoder */
+#define H64MX_SLAVE_DDRC_PORT0		3	/* DDR2 Port0-AESOTF */
+#define H64MX_SLAVE_DDRC_PORT1		4	/* DDR2 Port1 */
+#define H64MX_SLAVE_DDRC_PORT2		5	/* DDR2 Port2 */
+#define H64MX_SLAVE_DDRC_PORT3		6	/* DDR2 Port3 */
+#define H64MX_SLAVE_DDRC_PORT4		7	/* DDR2 Port4 */
+#define H64MX_SLAVE_DDRC_PORT5		8	/* DDR2 Port5 */
+#define H64MX_SLAVE_DDRC_PORT6		9	/* DDR2 Port6 */
+#define H64MX_SLAVE_DDRC_PORT7		10	/* DDR2 Port7 */
+#define H64MX_SLAVE_SRAM		11	/* Internal SRAM 128K */
+#define H64MX_SLAVE_H32MX_BRIDGE	12	/* Bridge from H64MX to H32MX */
+
+/* MATRIX1(H32MX) slave id definitions */
+#define H32MX_SLAVE_H64MX_BRIDGE	0	/* Bridge from H32MX to H64MX */
+#define H32MX_SLAVE_PERIPH_BRIDGE0	1	/* H32MX Peripheral Bridge 0 */
+#define H32MX_SLAVE_PERIPH_BRIDGE1	2	/* H32MX Peripheral Bridge 1 */
+#define H32MX_SLAVE_EBI			3	/* External Bus Interface */
+#define H32MX_SLAVE_NFC_CMD		3	/* NFC command Register */
+#define H32MX_SLAVE_NFC_SRAM		4	/* NFC SRAM */
+#define H32MX_SLAVE_USB			5	/* USB Device & Host */
+#define H32MX_SLAVE_SMD			6	/* Soft Modem (SMD) */
+
+/* AICREDIR Unlock Key */
+#define ATMEL_SFR_AICREDIR_KEY		0x5F67B102
+
 /* sama5d4 series chip id definitions */
 #define ARCH_ID_SAMA5D4		0x8a5c07c0
 #define ARCH_EXID_SAMA5D41	0x00000001
@@ -193,6 +216,9 @@
 #define cpu_is_sama5d44()	(cpu_is_sama5d4() && \
 		(get_extension_chip_id() == ARCH_EXID_SAMA5D44))
 
+/* Timer */
+#define CONFIG_SYS_TIMER_COUNTER	0xfc06863c
+
 /*
  * No PMECC Galois table in ROM
  */