X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fmach-at91%2Finclude%2Fmach%2Fat91_pmc.h;h=680ceb03145d6f8f0217d4ee52997f3dfd65b66c;hb=6beacfcff81bdc04c10a440971b0fb683ee57534;hp=ebb7decd22e6001ee92e62ff638b3e6210861e86;hpb=ff255e836a3a6cd52bd51a192af96ac5f224dc22;p=oweals%2Fu-boot.git

diff --git a/arch/arm/mach-at91/include/mach/at91_pmc.h b/arch/arm/mach-at91/include/mach/at91_pmc.h
index ebb7decd22..680ceb0314 100644
--- a/arch/arm/mach-at91/include/mach/at91_pmc.h
+++ b/arch/arm/mach-at91/include/mach/at91_pmc.h
@@ -51,19 +51,15 @@ typedef struct at91_pmc {
 	u32	imr;		/* 0x6C Interrupt Mask Register */
 	u32	reserved4[4];
 	u32	pllicpr;	/* 0x80 Change Pump Current Register (SAM9) */
-	u32	reserved5[21];
+	u32	reserved5[24];
 	u32	wpmr;		/* 0xE4 Write Protect Mode Register (CAP0) */
 	u32	wpsr;		/* 0xE8 Write Protect Status Register (CAP0) */
-#ifdef CPU_HAS_PCR
-	u32	reserved6[8];
+	u32	reserved6[5];
 	u32	pcer1;		/* 0x100 Periperial Clock Enable Register 1 */
 	u32	pcdr1;		/* 0x104 Periperial Clock Disable Register 1 */
 	u32	pcsr1;		/* 0x108 Periperial Clock Status Register 1 */
 	u32	pcr;		/* 0x10c Periperial Control Register */
 	u32	ocr;		/* 0x110 Oscillator Calibration Register */
-#else
-	u32	reserved8[5];
-#endif
 } at91_pmc_t;
 
 #endif	/* end not assembly */
@@ -71,17 +67,18 @@ typedef struct at91_pmc {
 #define AT91_PMC_MOR_MOSCEN		0x01
 #define AT91_PMC_MOR_OSCBYPASS		0x02
 #define AT91_PMC_MOR_MOSCRCEN		0x08
-#define AT91_PMC_MOR_OSCOUNT(x)		((x & 0xff) << 8)
-#define AT91_PMC_MOR_KEY(x)		((x & 0xff) << 16)
+#define AT91_PMC_MOR_OSCOUNT(x)		(((x) & 0xff) << 8)
+#define AT91_PMC_MOR_KEY(x)		(((x) & 0xff) << 16)
 #define AT91_PMC_MOR_MOSCSEL		(1 << 24)
 
-#define AT91_PMC_PLLXR_DIV(x)		(x & 0xFF)
-#define AT91_PMC_PLLXR_PLLCOUNT(x)	((x & 0x3F) << 8)
-#define AT91_PMC_PLLXR_OUT(x)		((x & 0x03) << 14)
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4)
-#define AT91_PMC_PLLXR_MUL(x)		((x & 0x7F) << 18)
+#define AT91_PMC_PLLXR_DIV(x)		((x) & 0xFF)
+#define AT91_PMC_PLLXR_PLLCOUNT(x)	(((x) & 0x3F) << 8)
+#define AT91_PMC_PLLXR_OUT(x)		(((x) & 0x03) << 14)
+#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \
+	defined(CONFIG_SAMA5D4)
+#define AT91_PMC_PLLXR_MUL(x)		(((x) & 0x7F) << 18)
 #else
-#define AT91_PMC_PLLXR_MUL(x)		((x & 0x7FF) << 16)
+#define AT91_PMC_PLLXR_MUL(x)		(((x) & 0x7FF) << 16)
 #endif
 #define AT91_PMC_PLLAR_29		0x20000000
 #define AT91_PMC_PLLBR_USBDIV_1		0x00000000
@@ -97,7 +94,8 @@ typedef struct at91_pmc {
 #define AT91_PMC_MCKR_CSS_PLLB		0x00000003
 #define AT91_PMC_MCKR_CSS_MASK		0x00000003
 
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
+#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D3) || \
+	defined(CONFIG_SAMA5D4) || \
 	defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
 #define AT91_PMC_MCKR_PRES_1		0x00000000
 #define AT91_PMC_MCKR_PRES_2		0x00000010
@@ -127,10 +125,7 @@ typedef struct at91_pmc {
 #else
 #define AT91_PMC_MCKR_MDIV_1		0x00000000
 #define AT91_PMC_MCKR_MDIV_2		0x00000100
-#if defined(CONFIG_SAMA5D3) || defined(CONFIG_SAMA5D4) || \
-	defined(CONFIG_AT91SAM9X5) || defined(CONFIG_AT91SAM9N12)
 #define AT91_PMC_MCKR_MDIV_3		0x00000300
-#endif
 #define AT91_PMC_MCKR_MDIV_4		0x00000200
 #define AT91_PMC_MCKR_MDIV_MASK		0x00000300
 #endif
@@ -153,11 +148,24 @@ typedef struct at91_pmc {
 #define AT91_PMC_IXR_MOSCSELS		0x00010000
 
 #define AT91_PMC_PCR_PID_MASK		(0x3f)
+#define AT91_PMC_PCR_GCKCSS		(0x7 << 8)
+#define		AT91_PMC_PCR_GCKCSS_SLOW_CLK	(0x0 << 8)
+#define		AT91_PMC_PCR_GCKCSS_MAIN_CLK	(0x1 << 8)
+#define		AT91_PMC_PCR_GCKCSS_PLLA_CLK	(0x2 << 8)
+#define		AT91_PMC_PCR_GCKCSS_UPLL_CLK	(0x3 << 8)
+#define		AT91_PMC_PCR_GCKCSS_MCK_CLK	(0x4 << 8)
+#define		AT91_PMC_PCR_GCKCSS_AUDIO_CLK	(0x5 << 8)
 #define AT91_PMC_PCR_CMD_WRITE		(0x1 << 12)
+#define AT91_PMC_PCR_DIV		(0x3 << 16)
+#define AT91_PMC_PCR_GCKDIV		(0xff << 20)
+#define		AT91_PMC_PCR_GCKDIV_(x)		(((x) & 0xff) << 20)
+#define		AT91_PMC_PCR_GCKDIV_OFFSET	20
 #define AT91_PMC_PCR_EN			(0x1 << 28)
+#define AT91_PMC_PCR_GCKEN		(0x1 << 29)
 
 #define		AT91_PMC_PCK		(1 <<  0)		/* Processor Clock */
 #define		AT91RM9200_PMC_UDP	(1 <<  1)		/* USB Devcice Port Clock [AT91RM9200 only] */
+#define		AT91_PMC_DDR		(1 <<  2)		/* DDR Clock */
 #define		AT91RM9200_PMC_MCKUDP	(1 <<  2)		/* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
 #define		AT91RM9200_PMC_UHP	(1 <<  4)		/* USB Host Port Clock [AT91RM9200 only] */
 #define		AT91SAM926x_PMC_UHP	(1 <<  6)		/* USB Host Port Clock [AT91SAM926x only] */
@@ -235,6 +243,14 @@ typedef struct at91_pmc {
 #define		AT91_PMC_PCK1RDY	(1 <<  9)		/* Programmable Clock 1 */
 #define		AT91_PMC_PCK2RDY	(1 << 10)		/* Programmable Clock 2 */
 #define		AT91_PMC_PCK3RDY	(1 << 11)		/* Programmable Clock 3 */
+#define		AT91_PMC_GCKRDY		(1 << 24)
 
 #define		AT91_PMC_PROTKEY	0x504d4301	/* Activation Code */
+
+/* PLL Charge Pump Current Register (PMC_PLLICPR) */
+#define AT91_PMC_ICP_PLLA(x)		(((x) & 0x3) << 0)
+#define AT91_PMC_IPLL_PLLA(x)		(((x) & 0x7) << 8)
+#define AT91_PMC_ICP_PLLU(x)		(((x) & 0x3) << 16)
+#define AT91_PMC_IVCO_PLLU(x)		(((x) & 0x3) << 24)
+
 #endif