X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Flib%2Frelocate.S;h=475d503dd9df63fda046d225c47205a1bc9c80af;hb=a60d94b204412732409e70cb15236bd96d4da7d9;hp=b4a258ce5c7917ca61bbaa5896036e57673f90d2;hpb=130aec779ad9a2e28dc9d42ca5b367b957f311d7;p=oweals%2Fu-boot.git

diff --git a/arch/arm/lib/relocate.S b/arch/arm/lib/relocate.S
index b4a258ce5c..475d503dd9 100644
--- a/arch/arm/lib/relocate.S
+++ b/arch/arm/lib/relocate.S
@@ -9,6 +9,60 @@
 #include <asm-offsets.h>
 #include <config.h>
 #include <linux/linkage.h>
+#ifdef CONFIG_CPU_V7M
+#include <asm/armv7m.h>
+#endif
+
+/*
+ * Default/weak exception vectors relocation routine
+ *
+ * This routine covers the standard ARM cases: normal (0x00000000),
+ * high (0xffff0000) and VBAR. SoCs which do not comply with any of
+ * the standard cases must provide their own, strong, version.
+ */
+
+	.section	.text.relocate_vectors,"ax",%progbits
+	.weak		relocate_vectors
+
+ENTRY(relocate_vectors)
+
+#ifdef CONFIG_CPU_V7M
+	/*
+	 * On ARMv7-M we only have to write the new vector address
+	 * to VTOR register.
+	 */
+	ldr	r0, [r9, #GD_RELOCADDR]	/* r0 = gd->relocaddr */
+	ldr	r1, =V7M_SCB_BASE
+	str	r0, [r1, V7M_SCB_VTOR]
+#else
+#ifdef CONFIG_HAS_VBAR
+	/*
+	 * If the ARM processor has the security extensions,
+	 * use VBAR to relocate the exception vectors.
+	 */
+	ldr	r0, [r9, #GD_RELOCADDR]	/* r0 = gd->relocaddr */
+	mcr     p15, 0, r0, c12, c0, 0  /* Set VBAR */
+#else
+	/*
+	 * Copy the relocated exception vectors to the
+	 * correct address
+	 * CP15 c1 V bit gives us the location of the vectors:
+	 * 0x00000000 or 0xFFFF0000.
+	 */
+	ldr	r0, [r9, #GD_RELOCADDR]	/* r0 = gd->relocaddr */
+	mrc	p15, 0, r2, c1, c0, 0	/* V bit (bit[13]) in CP15 c1 */
+	ands	r2, r2, #(1 << 13)
+	ldreq	r1, =0x00000000		/* If V=0 */
+	ldrne	r1, =0xFFFF0000		/* If V=1 */
+	ldmia	r0!, {r2-r8,r10}
+	stmia	r1!, {r2-r8,r10}
+	ldmia	r0!, {r2-r8,r10}
+	stmia	r1!, {r2-r8,r10}
+#endif
+#endif
+	bx	lr
+
+ENDPROC(relocate_vectors)
 
 /*
  * void relocate_code(addr_moni)
@@ -54,34 +108,6 @@ fixnext:
 	cmp	r2, r3
 	blo	fixloop
 
-	/*
-	 * Relocate the exception vectors
-	 */
-#ifdef CONFIG_HAS_VBAR
-	/*
-	 * If the ARM processor has the security extensions,
-	 * use VBAR to relocate the exception vectors.
-	 */
-	ldr	r0, [r9, #GD_RELOCADDR]	/* r0 = gd->relocaddr */
-	mcr     p15, 0, r0, c12, c0, 0  /* Set VBAR */
-#else
-	/*
-	 * Copy the relocated exception vectors to the
-	 * correct address
-	 * CP15 c1 V bit gives us the location of the vectors:
-	 * 0x00000000 or 0xFFFF0000.
-	 */
-	ldr	r0, [r9, #GD_RELOCADDR]	/* r0 = gd->relocaddr */
-	mrc	p15, 0, r2, c1, c0, 0	/* V bit (bit[13]) in CP15 c1 */
-	ands	r2, r2, #(1 << 13)
-	ldreq	r1, =0x00000000 	/* If V=0 */
-	ldrne	r1, =0xFFFF0000 	/* If V=1 */
-	ldmia	r0!, {r2-r8,r10}
-	stmia	r1!, {r2-r8,r10}
-	ldmia	r0!, {r2-r8,r10}
-	stmia	r1!, {r2-r8,r10}
-#endif
-
 relocate_done:
 
 #ifdef __XSCALE__
@@ -96,9 +122,9 @@ relocate_done:
 	/* ARMv4- don't know bx lr but the assembler fails to see that */
 
 #ifdef __ARM_ARCH_4__
-	mov        pc, lr
+	mov	pc, lr
 #else
-	bx        lr
+	bx	lr
 #endif
 
 ENDPROC(relocate_code)