X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Flib%2Fcache-cp15.c;h=e9bbcf51220fd6399eb8b5114d7228e5d9d4406b;hb=73eed452b9c9827474c0789c30729dca6fcf061d;hp=1121dc3a936c8ce5f1ee10314240136516d30b94;hpb=d990f5c834f1b42293fb53e4fd7f3aa988184196;p=oweals%2Fu-boot.git

diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 1121dc3a93..e9bbcf5122 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -61,16 +61,37 @@ __weak void mmu_page_table_flush(unsigned long start, unsigned long stop)
 void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
 				     enum dcache_option option)
 {
+#ifdef CONFIG_ARMV7_LPAE
+	u64 *page_table = (u64 *)gd->arch.tlb_addr;
+#else
 	u32 *page_table = (u32 *)gd->arch.tlb_addr;
+#endif
+	unsigned long startpt, stoppt;
 	unsigned long upto, end;
 
 	end = ALIGN(start + size, MMU_SECTION_SIZE) >> MMU_SECTION_SHIFT;
 	start = start >> MMU_SECTION_SHIFT;
-	debug("%s: start=%pa, size=%zu, option=%d\n", __func__, &start, size,
+#ifdef CONFIG_ARMV7_LPAE
+	debug("%s: start=%pa, size=%zu, option=%llx\n", __func__, &start, size,
 	      option);
+#else
+	debug("%s: start=%pa, size=%zu, option=0x%x\n", __func__, &start, size,
+	      option);
+#endif
 	for (upto = start; upto < end; upto++)
 		set_section_dcache(upto, option);
-	mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]);
+
+	/*
+	 * Make sure range is cache line aligned
+	 * Only CPU maintains page tables, hence it is safe to always
+	 * flush complete cache lines...
+	 */
+
+	startpt = (unsigned long)&page_table[start];
+	startpt &= ~(CONFIG_SYS_CACHELINE_SIZE - 1);
+	stoppt = (unsigned long)&page_table[end];
+	stoppt = ALIGN(stoppt, CONFIG_SYS_CACHELINE_SIZE);
+	mmu_page_table_flush(startpt, stoppt);
 }
 
 __weak void dram_bank_mmu_setup(int bank)