X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Fcache.h;h=ddebbc8fcdc40c937d43b8cf08f67959b7613384;hb=4a68d3431ace189746ffb498dc9e844296626615;hp=6d60a4a6d955d276d12a492bdcf59342882a7dc0;hpb=326ea986ac150acdc7656d57fca647db80b50158;p=oweals%2Fu-boot.git

diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index 6d60a4a6d9..ddebbc8fcd 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -11,6 +11,8 @@
 
 #include <asm/system.h>
 
+#ifndef CONFIG_ARM64
+
 /*
  * Invalidate L2 Cache using co-proc instruction
  */
@@ -28,6 +30,9 @@ void l2_cache_disable(void);
 void set_section_dcache(int section, enum dcache_option option);
 
 void dram_bank_mmu_setup(int bank);
+
+#endif
+
 /*
  * The current upper bound for ARM L1 data cache line sizes is 64 bytes.  We
  * use that value for aligning DMA buffers unless the board config has specified