X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Fcache.h;h=a836e9f2ab2838807d0a53c801b8c5f722eb5b76;hb=2aacc4239c32aa732621f3a432d576c68c3016d8;hp=8153484899106f456b1cf928307cc4cae4453012;hpb=8dc16cf9dd6196d99969d12741df186a61a2f9a3;p=oweals%2Fu-boot.git diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 8153484899..a836e9f2ab 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -3,23 +3,7 @@ * Marvell Semiconductor * Written-by: Prafulla Wadaskar * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _ASM_CACHE_H @@ -27,6 +11,8 @@ #include +#ifndef CONFIG_ARM64 + /* * Invalidate L2 Cache using co-proc instruction */ @@ -43,7 +29,13 @@ void l2_cache_enable(void); void l2_cache_disable(void); void set_section_dcache(int section, enum dcache_option option); +void arm_init_before_mmu(void); +void arm_init_domains(void); +void cpu_cache_initialization(void); void dram_bank_mmu_setup(int bank); + +#endif + /* * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We * use that value for aligning DMA buffers unless the board config has specified