X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-sunxi%2Fcpu_sun9i.h;h=c775bcc515a0a269dfc36b9ce8fa5f91a6aef3ce;hb=04770e6e917b0f766a9496e3f37bcdf2ebb1beb4;hp=a2a7839c6bdfcf014710e697eef6b66f8dde9f33;hpb=3b95288a2ae8146ca4915250f815c1218b1706fa;p=oweals%2Fu-boot.git

diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
index a2a7839c6b..c775bcc515 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun9i.h
@@ -23,6 +23,10 @@
 #define SUNXI_NFC_BASE			(REGS_AHB0_BASE + 0x3000)
 #define SUNXI_TSC_BASE			(REGS_AHB0_BASE + 0x4000)
 
+#define SUNXI_GTBUS_BASE		(REGS_AHB0_BASE + 0x9000)
+/* SID address space starts at 0x01ce000, but e-fuse is at offset 0x200 */
+#define SUNXI_SID_BASE			(REGS_AHB0_BASE + 0xe200)
+
 #define SUNXI_MMC0_BASE			(REGS_AHB0_BASE + 0x0f000)
 #define SUNXI_MMC1_BASE			(REGS_AHB0_BASE + 0x10000)
 #define SUNXI_MMC2_BASE			(REGS_AHB0_BASE + 0x11000)
@@ -38,6 +42,12 @@
 #define SUNXI_ARMA9_GIC_BASE		(REGS_AHB0_BASE + 0x41000)
 #define SUNXI_ARMA9_CPUIF_BASE		(REGS_AHB0_BASE + 0x42000)
 
+#define SUNXI_DRAM_COM_BASE		(REGS_AHB0_BASE + 0x62000)
+#define SUNXI_DRAM_CTL0_BASE		(REGS_AHB0_BASE + 0x63000)
+#define SUNXI_DRAM_CTL1_BASE		(REGS_AHB0_BASE + 0x64000)
+#define SUNXI_DRAM_PHY0_BASE		(REGS_AHB0_BASE + 0x65000)
+#define SUNXI_DRAM_PHY1_BASE		(REGS_AHB0_BASE + 0x66000)
+
 /* AHB1 Module */
 #define SUNXI_DMA_BASE			(REGS_AHB1_BASE + 0x002000)
 #define SUNXI_USBOTG_BASE		(REGS_AHB1_BASE + 0x100000)
@@ -73,7 +83,6 @@
 #define SUNXI_CCM_BASE			(REGS_APB0_BASE + 0x0000)
 #define SUNXI_CCMMODULE_BASE		(REGS_APB0_BASE + 0x0400)
 #define SUNXI_PIO_BASE			(REGS_APB0_BASE + 0x0800)
-#define SUNXI_R_PIO_BASE		(0x08002C00)
 #define SUNXI_TIMER_BASE		(REGS_APB0_BASE + 0x0C00)
 #define SUNXI_PWM_BASE			(REGS_APB0_BASE + 0x1400)
 #define SUNXI_LRADC_BASE		(REGS_APB0_BASE + 0x1800)
@@ -92,8 +101,10 @@
 #define SUNXI_TWI4_BASE			(REGS_APB1_BASE + 0x3800)
 
 /* RCPUS Module */
-#define SUNXI_RPRCM_BASE		(REGS_RCPUS_BASE + 0x1400)
+#define SUNXI_PRCM_BASE			(REGS_RCPUS_BASE + 0x1400)
 #define SUNXI_R_UART_BASE		(REGS_RCPUS_BASE + 0x2800)
+#define SUNXI_R_PIO_BASE		(REGS_RCPUS_BASE + 0x2c00)
+#define SUNXI_RSB_BASE			(REGS_RCPUS_BASE + 0x3400)
 
 /* Misc. */
 #define SUNXI_BROM_BASE			0xFFFF0000 /* 32K */