X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-mxs%2Fregs-clkctrl-mx28.h;h=caef9e4b1fc7cc313ada6496a93a41d88f32befd;hb=d8a3f5259a36e76d1de127f65714c40918e8ee4c;hp=b662fbe440049cbb2d9a7743d099c29f867d57b1;hpb=6e2fbdea1b26d75314d87c380a36b0015bf824cf;p=oweals%2Fu-boot.git

diff --git a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
index b662fbe440..caef9e4b1f 100644
--- a/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
+++ b/arch/arm/include/asm/arch-mxs/regs-clkctrl-mx28.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Freescale i.MX28 CLKCTRL Register Definitions
  *
@@ -6,44 +7,36 @@
  *
  * Based on code from LTIB:
  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- *
  */
 
 #ifndef __MX28_REGS_CLKCTRL_H__
 #define __MX28_REGS_CLKCTRL_H__
 
-#include <asm/arch/regs-common.h>
+#include <asm/mach-imx/regs-common.h>
 
 #ifndef	__ASSEMBLY__
 struct mxs_clkctrl_regs {
 	mxs_reg_32(hw_clkctrl_pll0ctrl0)	/* 0x00 */
-	mxs_reg_32(hw_clkctrl_pll0ctrl1)	/* 0x10 */
+	uint32_t	hw_clkctrl_pll0ctrl1;	/* 0x10 */
+	uint32_t	reserved_pll0ctrl1[3];	/* 0x14-0x1c */
 	mxs_reg_32(hw_clkctrl_pll1ctrl0)	/* 0x20 */
-	mxs_reg_32(hw_clkctrl_pll1ctrl1)	/* 0x30 */
+	uint32_t	hw_clkctrl_pll1ctrl1;	/* 0x30 */
+	uint32_t	reserved_pll1ctrl1[3];	/* 0x34-0x3c */
 	mxs_reg_32(hw_clkctrl_pll2ctrl0)	/* 0x40 */
 	mxs_reg_32(hw_clkctrl_cpu)		/* 0x50 */
 	mxs_reg_32(hw_clkctrl_hbus)		/* 0x60 */
 	mxs_reg_32(hw_clkctrl_xbus)		/* 0x70 */
 	mxs_reg_32(hw_clkctrl_xtal)		/* 0x80 */
-	mxs_reg_32(hw_clkctrl_ssp0)		/* 0x90 */
-	mxs_reg_32(hw_clkctrl_ssp1)		/* 0xa0 */
-	mxs_reg_32(hw_clkctrl_ssp2)		/* 0xb0 */
-	mxs_reg_32(hw_clkctrl_ssp3)		/* 0xc0 */
-	mxs_reg_32(hw_clkctrl_gpmi)		/* 0xd0 */
+	uint32_t	hw_clkctrl_ssp0;	/* 0x90 */
+	uint32_t	reserved_ssp0[3];	/* 0x94-0x9c */
+	uint32_t	hw_clkctrl_ssp1;	/* 0xa0 */
+	uint32_t	reserved_ssp1[3];	/* 0xa4-0xac */
+	uint32_t	hw_clkctrl_ssp2;	/* 0xb0 */
+	uint32_t	reserved_ssp2[3];	/* 0xb4-0xbc */
+	uint32_t	hw_clkctrl_ssp3;	/* 0xc0 */
+	uint32_t	reserved_ssp3[3];	/* 0xc4-0xcc */
+	uint32_t	hw_clkctrl_gpmi;	/* 0xd0 */
+	uint32_t	reserved_gpmi[3];	/* 0xd4-0xdc */
 	mxs_reg_32(hw_clkctrl_spdif)		/* 0xe0 */
 	mxs_reg_32(hw_clkctrl_emi)		/* 0xf0 */
 	mxs_reg_32(hw_clkctrl_saif0)		/* 0x100 */