X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-mx6%2Fcrm_regs.h;h=22212c2202ea399edbdffdc12e7c3b409ba5403c;hb=008e61f5120e7d3acb937953b1322e3aee3160d4;hp=720207303b01adbd34f94eba215468d9c0a408c6;hpb=c0cae2e24552d57f3e2f841ec235453413cd7389;p=oweals%2Fu-boot.git diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 720207303b..22212c2202 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -89,7 +89,7 @@ struct mxc_ccm_reg { u32 analog_pll_video_tog; u32 analog_pll_video_num; /* 0x40b0 */ u32 analog_reserved6[3]; - u32 analog_pll_vedio_denon; /* 0x40c0 */ + u32 analog_pll_video_denom; /* 0x40c0 */ u32 analog_reserved7[7]; u32 analog_pll_enet; /* 0x40e0 */ u32 analog_pll_enet_set; @@ -103,6 +103,97 @@ struct mxc_ccm_reg { u32 analog_pfd_528_set; u32 analog_pfd_528_clr; u32 analog_pfd_528_tog; + /* PMU Memory Map/Register Definition */ + u32 pmu_reg_1p1; + u32 pmu_reg_1p1_set; + u32 pmu_reg_1p1_clr; + u32 pmu_reg_1p1_tog; + u32 pmu_reg_3p0; + u32 pmu_reg_3p0_set; + u32 pmu_reg_3p0_clr; + u32 pmu_reg_3p0_tog; + u32 pmu_reg_2p5; + u32 pmu_reg_2p5_set; + u32 pmu_reg_2p5_clr; + u32 pmu_reg_2p5_tog; + u32 pmu_reg_core; + u32 pmu_reg_core_set; + u32 pmu_reg_core_clr; + u32 pmu_reg_core_tog; + u32 pmu_misc0; + u32 pmu_misc0_set; + u32 pmu_misc0_clr; + u32 pmu_misc0_tog; + u32 pmu_misc1; + u32 pmu_misc1_set; + u32 pmu_misc1_clr; + u32 pmu_misc1_tog; + u32 pmu_misc2; + u32 pmu_misc2_set; + u32 pmu_misc2_clr; + u32 pmu_misc2_tog; + /* TEMPMON Memory Map/Register Definition */ + u32 tempsense0; + u32 tempsense0_set; + u32 tempsense0_clr; + u32 tempsense0_tog; + u32 tempsense1; + u32 tempsense1_set; + u32 tempsense1_clr; + u32 tempsense1_tog; + /* USB Analog Memory Map/Register Definition */ + u32 usb1_vbus_detect; + u32 usb1_vbus_detect_set; + u32 usb1_vbus_detect_clr; + u32 usb1_vbus_detect_tog; + u32 usb1_chrg_detect; + u32 usb1_chrg_detect_set; + u32 usb1_chrg_detect_clr; + u32 usb1_chrg_detect_tog; + u32 usb1_vbus_det_stat; + u32 usb1_vbus_det_stat_set; + u32 usb1_vbus_det_stat_clr; + u32 usb1_vbus_det_stat_tog; + u32 usb1_chrg_det_stat; + u32 usb1_chrg_det_stat_set; + u32 usb1_chrg_det_stat_clr; + u32 usb1_chrg_det_stat_tog; + u32 usb1_loopback; + u32 usb1_loopback_set; + u32 usb1_loopback_clr; + u32 usb1_loopback_tog; + u32 usb1_misc; + u32 usb1_misc_set; + u32 usb1_misc_clr; + u32 usb1_misc_tog; + u32 usb2_vbus_detect; + u32 usb2_vbus_detect_set; + u32 usb2_vbus_detect_clr; + u32 usb2_vbus_detect_tog; + u32 usb2_chrg_detect; + u32 usb2_chrg_detect_set; + u32 usb2_chrg_detect_clr; + u32 usb2_chrg_detect_tog; + u32 usb2_vbus_det_stat; + u32 usb2_vbus_det_stat_set; + u32 usb2_vbus_det_stat_clr; + u32 usb2_vbus_det_stat_tog; + u32 usb2_chrg_det_stat; + u32 usb2_chrg_det_stat_set; + u32 usb2_chrg_det_stat_clr; + u32 usb2_chrg_det_stat_tog; + u32 usb2_loopback; + u32 usb2_loopback_set; + u32 usb2_loopback_clr; + u32 usb2_loopback_tog; + u32 usb2_misc; + u32 usb2_misc_set; + u32 usb2_misc_clr; + u32 usb2_misc_tog; + u32 digprog; + u32 reserved1[7]; + /* For i.MX 6SoloLite */ + u32 digprog_sololite; }; #endif @@ -110,15 +201,22 @@ struct mxc_ccm_reg { #define MXC_CCM_CCR_RBC_EN (1 << 27) #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21) #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21 +/* CCR_WB does not exist on i.MX6SX/UL */ #define MXC_CCM_CCR_WB_COUNT_MASK 0x7 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16) #define MXC_CCM_CCR_COSC_EN (1 << 12) +#ifdef CONFIG_MX6SX +#define MXC_CCM_CCR_OSCNT_MASK 0x7F +#else #define MXC_CCM_CCR_OSCNT_MASK 0xFF +#endif #define MXC_CCM_CCR_OSCNT_OFFSET 0 /* Define the bits in register CCDR */ #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16) #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17) +/* Exists on i.MX6QP */ +#define MXC_CCM_CCDR_MMDC_CH1_AXI_ROOT_CG (1 << 18) /* Define the bits in register CSR */ #define MXC_CCM_CSR_COSC_READY (1 << 5) @@ -144,8 +242,9 @@ struct mxc_ccm_reg { /* Define the bits in register CBCDR */ #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27) #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27 -#define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26) +#define MXC_CCM_CBCDR_PERIPH2_CLK_SEL (1 << 26) #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25) +/* MMDC_CH0 not exists on i.MX6SX */ #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19) #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16) @@ -166,37 +265,54 @@ struct mxc_ccm_reg { #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 +/* LCDIF on i.MX6SX/UL */ +#define MXC_CCM_CBCMR_LCDIF1_PODF_MASK (0x7 << 23) +#define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET 23 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21 -#define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20) +#define MXC_CCM_CBCMR_PERIPH2_CLK2_SEL (1 << 20) #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18) #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18 +#ifndef CONFIG_MX6SX #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16) #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14) #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14 +#endif #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12) #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12 +#ifndef CONFIG_MX6SX #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11) +#endif #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10) #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8) #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4) #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4 -#define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1) -#define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0) +/* Exists on i.MX6QP */ +#define MXC_CCM_CBCMR_PRE_CLK_SEL (1 << 1) /* Define the bits in register CSCMR1 */ #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29) #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29 +/* QSPI1 exist on i.MX6SX/UL */ +#define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26) +#define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27) #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 +/* LCFIF2_PODF on i.MX6SX */ +#define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK (0x7 << 20) +#define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET 20 +/* ACLK_EMI on i.MX6DQ/SDL/DQP */ #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 +/* CSCMR1_GPMI/BCH exist on i.MX6UL */ +#define MXC_CCM_CSCMR1_GPMI_CLK_SEL (1 << 19) +#define MXC_CCM_CSCMR1_BCH_CLK_SEL (1 << 18) #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19) #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18) #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17) @@ -207,19 +323,42 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10) #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10 +/* QSPI1 exist on i.MX6SX/UL */ +#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7) +#define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7 +/* CSCMR1_PER_CLK exists on i.MX6SX/SL/QP */ +#define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6) +#define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6 + #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F /* Define the bits in register CSCMR2 */ +#ifdef CONFIG_MX6SX +#define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << 21) +#define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21 +#endif #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19) #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11) #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10) -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2) -#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2 +/* CSCMR1_CAN_CLK exists on i.MX6SX/QP */ +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8) +#define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8 + +#define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2) +#define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2 /* Define the bits in register CSCDR1 */ +#ifndef CONFIG_MX6SX #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25) #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25 +#endif +/* CSCDR1_GPMI/BCH exist on i.MX6UL */ +#define MXC_CCM_CSCDR1_GPMI_PODF_MASK (0x7 << 22) +#define MXC_CCM_CSCDR1_GPMI_PODF_OFFSET 22 +#define MXC_CCM_CSCDR1_BCH_PODF_MASK (0x7 << 19) +#define MXC_CCM_CSCDR1_BCH_PODF_OFFSET 19 + #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22) #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19) @@ -228,21 +367,22 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11) #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11 +#ifndef CONFIG_MX6SX #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8) #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6) -#ifdef CONFIG_MX6SL -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x1F -#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) -#else -#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F #endif +#define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0 +/* UART_CLK_SEL exists on i.MX6SL/SX/QP */ +#define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6) /* Define the bits in register CS1CDR */ #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25) #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25 +#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22) +#define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16) #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9) @@ -253,15 +393,44 @@ struct mxc_ccm_reg { #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0 /* Define the bits in register CS2CDR */ +/* QSPI2 on i.MX6SX */ +#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21) +#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21 +#define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21) +#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << 18) +#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18 +#define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18) +#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15) +#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15 +#define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15) + #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21) #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21) #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18) #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18) -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16) -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16 -#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << 16) + +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP (0x7 << 15) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP 15 +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) (((v) & 0x7) << 15) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ (0x3 << 16) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ 16 +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v) (((v) & 0x3) << 16) + +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK \ + ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQP : \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK_DQ) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET \ + ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQP : \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET_DQ) +#define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) \ + ((is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) ? \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQP(v) : \ + MXC_CCM_CS2CDR_ENFC_CLK_SEL_DQ(v)) + #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12) #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9) @@ -272,13 +441,15 @@ struct mxc_ccm_reg { #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0 /* Define the bits in register CDCDR */ +#ifndef CONFIG_MX6SX #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29) #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28) +#endif #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25) #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25 -#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19) -#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19 +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 22) +#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 22 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20) #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12) @@ -289,6 +460,20 @@ struct mxc_ccm_reg { #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7 /* Define the bits in register CHSCCDR */ +#ifdef CONFIG_MX6SX +#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15) +#define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15 +#define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12) +#define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12 +#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << 9) +#define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9 +#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << 6) +#define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6 +#define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << 3) +#define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3 +#define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7) +#define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0 +#else #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15) #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12) @@ -301,6 +486,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7) #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0 +#endif #define CHSCCDR_CLK_SEL_LDB_DI0 3 #define CHSCCDR_PODF_DIVIDE_BY_3 2 @@ -309,12 +495,31 @@ struct mxc_ccm_reg { /* Define the bits in register CSCDR2 */ #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19) #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 +/* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */ +#define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18) +/* LCDIF1 on i.MX6SX/UL */ +#define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK (0x7 << 15) +#define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET 15 +#define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK (0x7 << 12) +#define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET 12 +#define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK (0x7 << 9) +#define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET 9 +/* LCDIF2 on i.MX6SX */ +#define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK (0x7 << 6) +#define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET 6 +#define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK (0x7 << 3) +#define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET 3 +#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK (0x7 << 0) +#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET 0 + +/* All IPU2_DI1 are LCDIF1 on MX6SX */ #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12) #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9) #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9 +/* All IPU2_DI0 are LCDIF2 on MX6SX */ #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6) #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3) @@ -335,7 +540,9 @@ struct mxc_ccm_reg { /* Define the bits in register CDHIPR */ #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16) #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5) +#ifndef CONFIG_MX6SX #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4) +#endif #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3) #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2) #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1) @@ -344,14 +551,18 @@ struct mxc_ccm_reg { /* Define the bits in register CLPCR */ #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27) #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26) +#ifndef CONFIG_MX6SX #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25) #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24) #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23) +#endif #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22) #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21) +#ifndef CONFIG_MX6SX #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19) #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17) -#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17) +#endif +#define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 16) #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11) #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9) #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9 @@ -359,15 +570,19 @@ struct mxc_ccm_reg { #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7) #define MXC_CCM_CLPCR_SBYOS (1 << 6) #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5) +#ifndef CONFIG_MX6SX #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3) #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2) +#endif #define MXC_CCM_CLPCR_LPM_MASK 0x3 #define MXC_CCM_CLPCR_LPM_OFFSET 0 /* Define the bits in register CISR */ #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26) +#ifndef CONFIG_MX6SX #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23) +#endif #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22) #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21) #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20) @@ -378,11 +593,13 @@ struct mxc_ccm_reg { /* Define the bits in register CIMR */ #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26) +#ifndef CONFIG_MX6SX #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23) +#endif #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22) #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21) #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20) -#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22) +#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 19) #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17) #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6) #define MXC_CCM_CIMR_MASK_LRF_PLL 1 @@ -393,6 +610,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16) +#define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8) #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7) #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4) #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4 @@ -400,6 +618,7 @@ struct mxc_ccm_reg { #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0 /* Define the bits in registers CGPR */ +#define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16) #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4) #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2) #define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1 @@ -435,8 +654,13 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET) #define MXC_CCM_CCGR0_DCIC2_OFFSET 26 #define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET) +#ifdef CONFIG_MX6SX +#define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30 +#define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET) +#else #define MXC_CCM_CCGR0_DTCP_OFFSET 28 #define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET) +#endif #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET) @@ -448,33 +672,55 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET) #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET) -#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10 -#define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET) +/* CCGR1_ENET does not exist on i.MX6SX/UL */ +#define MXC_CCM_CCGR1_ENET_OFFSET 10 +#define MXC_CCM_CCGR1_ENET_MASK (3 << MXC_CCM_CCGR1_ENET_OFFSET) #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12 #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET) #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14 #define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET) #define MXC_CCM_CCGR1_ESAIS_OFFSET 16 #define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET) +#ifdef CONFIG_MX6SX +#define MXC_CCM_CCGR1_WAKEUP_OFFSET 18 +#define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET) +#endif #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET) #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET) +#ifndef CONFIG_MX6SX #define MXC_CCM_CCGR1_GPU2D_OFFSET 24 #define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET) +#endif #define MXC_CCM_CCGR1_GPU3D_OFFSET 26 #define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET) +#ifdef CONFIG_MX6SX +#define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28 +#define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET) +#define MXC_CCM_CCGR1_CANFD_OFFSET 30 +#define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET) +#endif +#ifndef CONFIG_MX6SX #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET) +#else +#define MXC_CCM_CCGR2_CSI_OFFSET 2 +#define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET) +#endif +#ifndef CONFIG_MX6SX #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET) +#endif #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET) #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET) #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET) +#define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET 8 +#define MXC_CCM_CCGR1_I2C4_SERIAL_MASK (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET) #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET) #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14 @@ -487,17 +733,32 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET) #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET) +/* i.MX6SX/UL LCD and PXP */ +#define MXC_CCM_CCGR2_LCD_OFFSET 28 +#define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET) +#define MXC_CCM_CCGR2_PXP_OFFSET 30 +#define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET) + #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET) #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET) +/* Exist on i.MX6SX */ +#define MXC_CCM_CCGR3_M4_OFFSET 2 +#define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET) +#define MXC_CCM_CCGR3_ENET_OFFSET 4 +#define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET) +#define MXC_CCM_CCGR3_QSPI_OFFSET 14 +#define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET) + #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET) #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET) #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET) + #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET) #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8 @@ -506,27 +767,61 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET) #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET) + +/* QSPI1 exists on i.MX6SX/UL */ +#define MXC_CCM_CCGR3_QSPI1_OFFSET 14 +#define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET) + #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET) #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET) + +/* A7_CLKDIV/WDOG1 on i.MX6UL */ +#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET 16 +#define MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR3_WDOG1_CLK_ENABLE_OFFSET) +#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET 18 +#define MXC_CCM_CCGR3_A7_CLKDIV_PATCH_MASK (3 << MXC_CCM_CCGR3_A7_CLKDIV_PATCH_OFFSET) + #define MXC_CCM_CCGR3_MLB_OFFSET 18 #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET) #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET) +#ifndef CONFIG_MX6SX #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET) +#endif #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET) #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET) + +#define MXC_CCM_CCGR3_DISP_AXI_OFFSET 6 +#define MXC_CCM_CCGR3_DISP_AXI_MASK (3 << MXC_CCM_CCGR3_DISP_AXI_OFFSET) +#define MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET 8 +#define MXC_CCM_CCGR3_LCDIF2_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET) +#define MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET 10 +#define MXC_CCM_CCGR3_LCDIF1_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET) +/* AXI on i.MX6UL */ +#define MXC_CCM_CCGR3_AXI_CLK_OFFSET 28 +#define MXC_CCM_CCGR3_AXI_CLK_MASK (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET) #define MXC_CCM_CCGR3_OCRAM_OFFSET 28 #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET) + +/* GPIO4 on i.MX6UL */ +#define MXC_CCM_CCGR3_GPIO4_CLK_OFFSET 30 +#define MXC_CCM_CCGR3_GPIO4_CLK_MASK (3 << MXC_CCM_CCGR3_GPIO4_CLK_OFFSET) + +#ifndef CONFIG_MX6SX #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET) +#endif #define MXC_CCM_CCGR4_PCIE_OFFSET 0 #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET) +/* QSPI2 on i.MX6SX */ +#define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10 +#define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET) #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET) #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12 @@ -552,8 +847,10 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR5_ROM_OFFSET 0 #define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET) +#ifndef CONFIG_MX6SX #define MXC_CCM_CCGR5_SATA_OFFSET 4 #define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET) +#endif #define MXC_CCM_CCGR5_SDMA_OFFSET 6 #define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET) #define MXC_CCM_CCGR5_SPBA_OFFSET 12 @@ -570,6 +867,15 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET) #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET) +#ifdef CONFIG_MX6SX +#define MXC_CCM_CCGR5_SAI1_OFFSET 20 +#define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET) +#define MXC_CCM_CCGR5_SAI2_OFFSET 30 +#define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET) +#endif + +/* PRG_CLK0 exists on i.MX6QP */ +#define MXC_CCM_CCGR6_PRG_CLK0_MASK (3 << 24) #define MXC_CCM_CCGR6_USBOH3_OFFSET 0 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET) @@ -577,12 +883,34 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET) #define MXC_CCM_CCGR6_USDHC2_OFFSET 4 #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET) +/* GPMI/BCH on i.MX6UL */ +#define MXC_CCM_CCGR6_BCH_OFFSET 6 +#define MXC_CCM_CCGR6_BCH_MASK (3 << MXC_CCM_CCGR6_BCH_OFFSET) +#define MXC_CCM_CCGR6_GPMI_OFFSET 8 +#define MXC_CCM_CCGR6_GPMI_MASK (3 << MXC_CCM_CCGR6_GPMI_OFFSET) + #define MXC_CCM_CCGR6_USDHC3_OFFSET 6 #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET) #define MXC_CCM_CCGR6_USDHC4_OFFSET 8 #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET) #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET) +/* The following *CCGR6* exist only i.MX6SX */ +#define MXC_CCM_CCGR6_PWM8_OFFSET 16 +#define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET) +#define MXC_CCM_CCGR6_VADC_OFFSET 20 +#define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET) +#define MXC_CCM_CCGR6_GIS_OFFSET 22 +#define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET) +#define MXC_CCM_CCGR6_I2C4_OFFSET 24 +#define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET) +#define MXC_CCM_CCGR6_PWM5_OFFSET 26 +#define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET) +#define MXC_CCM_CCGR6_PWM6_OFFSET 28 +#define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET) +#define MXC_CCM_CCGR6_PWM7_OFFSET 30 +#define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET) +/* The two does not exist on i.MX6SX */ #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET) @@ -761,10 +1089,10 @@ struct mxc_ccm_reg { #define BF_ANADIG_PLL_VIDEO_RSVD0(v) \ (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0) #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000 -#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19 -#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000 -#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \ - (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT) +#define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT 19 +#define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000 +#define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v) \ + (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000 #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000 @@ -811,6 +1139,7 @@ struct mxc_ccm_reg { #define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000 #define BF_ANADIG_PLL_ENET_RSVD1(v) \ (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1) +#define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000 #define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000 @@ -840,6 +1169,12 @@ struct mxc_ccm_reg { #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \ (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT) +/* ENET2 for i.MX6SX/UL */ +#define BM_ANADIG_PLL_ENET2_ENABLE 0x00100000 +#define BM_ANADIG_PLL_ENET2_DIV_SELECT 0x0000000C +#define BF_ANADIG_PLL_ENET2_DIV_SELECT(v) \ + (((v) << 2) & BM_ANADIG_PLL_ENET2_DIV_SELECT) + #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000 #define BP_ANADIG_PFD_480_PFD3_FRAC 24 @@ -890,4 +1225,18 @@ struct mxc_ccm_reg { #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) +#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008 + +#define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23) +#define BP_PMU_MISC2_AUDIO_DIV_MSB 23 + +#define BM_PMU_MISC2_AUDIO_DIV_LSB (1 << 15) +#define BP_PMU_MISC2_AUDIO_DIV_LSB 15 + +#define PMU_MISC2_AUDIO_DIV(v) \ + (((v & BM_PMU_MISC2_AUDIO_DIV_MSB) >> \ + (BP_PMU_MISC2_AUDIO_DIV_MSB - 1)) | \ + ((v & BM_PMU_MISC2_AUDIO_DIV_LSB) >> \ + BP_PMU_MISC2_AUDIO_DIV_LSB)) + #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */