X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Finclude%2Fasm%2Farch-mx31%2Fimx-regs.h;h=f23350e5c25115b5c3204ab26c3e418659fbc65e;hb=6ee3d00d1d9d9977e975bd72c3668ee4f210a99d;hp=8fd3d08069be2ce96bf708c3e14a05ab75185738;hpb=bd23b22badadcdc414a900828253961fc5ec6c39;p=oweals%2Fu-boot.git

diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 8fd3d08069..f23350e5c2 100644
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -1,24 +1,7 @@
 /*
- *
  * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #ifndef __ASM_ARCH_MX31_IMX_REGS_H
@@ -68,18 +51,7 @@ struct cspi_regs {
 	u32 test;
 };
 
-/* Watchdog Timer (WDOG) registers */
-#define WDOG_ENABLE	(1 << 2)
-#define WDOG_WT_SHIFT	8
-#define WDOG_WDZST	(1 << 0)
-
-struct wdog_regs {
-	u16 wcr;	/* Control */
-	u16 wsr;	/* Service */
-	u16 wrsr;	/* Reset Status */
-};
-
-/* IIM Control Registers */
+/* IIM control registers */
 struct iim_regs {
 	u32 iim_stat;
 	u32 iim_statm;
@@ -91,11 +63,28 @@ struct iim_regs {
 	u32 iim_sdat;
 	u32 iim_prev;
 	u32 iim_srev;
-	u32 iim_prog_p;
+	u32 iim_prg_p;
 	u32 iim_scs0;
 	u32 iim_scs1;
 	u32 iim_scs2;
 	u32 iim_scs3;
+	u32 res[0x1f1];
+	struct fuse_bank {
+		u32 fuse_regs[0x20];
+		u32 fuse_rsvd[0xe0];
+	} bank[3];
+};
+
+struct fuse_bank0_regs {
+	u32 fuse0_5[6];
+	u32 usr;
+	u32 fuse7_15[9];
+};
+
+struct fuse_bank2_regs {
+	u32 fuse0;
+	u32 uid[8];
+	u32 fuse9_15[7];
 };
 
 struct iomuxc_regs {
@@ -568,6 +557,7 @@ struct esdc_regs {
 #define CCMR_CKIH	(2 << 1)
 
 #define MX31_IIM_BASE_ADDR	0x5001C000
+#define IIM_BASE_ADDR		MX31_IIM_BASE_ADDR
 
 #define PDR0_CSI_PODF(x)	(((x) & 0x3f) << 26)
 #define PDR0_CSI_PRDF(x)	(((x) & 0x7) << 23)
@@ -687,7 +677,7 @@ struct esdc_regs {
 
 #define ARM_PPMRR		0x40000015
 
-#define WDOG_BASE		0x53FDC000
+#define WDOG1_BASE_ADDR		0x53FDC000
 
 /*
  * GPIO
@@ -895,32 +885,7 @@ struct esdc_regs {
 
 #define MX31_AIPS1_BASE_ADDR	0x43f00000
 #define IMX_USB_BASE		(MX31_AIPS1_BASE_ADDR + 0x88000)
-
-/* USB portsc */
-/* values for portsc field */
-#define MXC_EHCI_PHY_LOW_POWER_SUSPEND	(1 << 23)
-#define MXC_EHCI_FORCE_FS		(1 << 24)
-#define MXC_EHCI_UTMI_8BIT		(0 << 28)
-#define MXC_EHCI_UTMI_16BIT		(1 << 28)
-#define MXC_EHCI_SERIAL			(1 << 29)
-#define MXC_EHCI_MODE_UTMI		(0 << 30)
-#define MXC_EHCI_MODE_PHILIPS		(1 << 30)
-#define MXC_EHCI_MODE_ULPI		(2 << 30)
-#define MXC_EHCI_MODE_SERIAL		(3 << 30)
-
-/* values for flags field */
-#define MXC_EHCI_INTERFACE_DIFF_UNI	(0 << 0)
-#define MXC_EHCI_INTERFACE_DIFF_BI	(1 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_UNI	(2 << 0)
-#define MXC_EHCI_INTERFACE_SINGLE_BI	(3 << 0)
-#define MXC_EHCI_INTERFACE_MASK		(0xf)
-
-#define MXC_EHCI_POWER_PINS_ENABLED	(1 << 5)
-#define MXC_EHCI_TTL_ENABLED		(1 << 6)
-
-#define MXC_EHCI_INTERNAL_PHY		(1 << 7)
-#define MXC_EHCI_IPPUE_DOWN		(1 << 8)
-#define MXC_EHCI_IPPUE_UP		(1 << 9)
+#define IMX_USB_PORT_OFFSET	0x200
 
 /*
  * CSPI register definitions