X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fimx-common%2Fcache.c;h=b77548821dbbbea8909e395b6c56967bc6c08b5f;hb=cbe7706ab8aab06c18edaa9b120371f9c8012728;hp=54b021cfede98eeb3f74fb66d629a8b5a6f445fa;hpb=13a3972585af60ec367d209cedbd3601e0c77467;p=oweals%2Fu-boot.git

diff --git a/arch/arm/imx-common/cache.c b/arch/arm/imx-common/cache.c
index 54b021cfed..b77548821d 100644
--- a/arch/arm/imx-common/cache.c
+++ b/arch/arm/imx-common/cache.c
@@ -42,6 +42,12 @@ void v7_outer_cache_enable(void)
 	unsigned int val;
 
 
+	/*
+	 * Must disable the L2 before changing the latency parameters
+	 * and auxiliary control register.
+	 */
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
 	/*
 	 * Set bit 22 in the auxiliary control register. If this bit
 	 * is cleared, PL310 treats Normal Shared Non-cacheable
@@ -59,9 +65,6 @@ void v7_outer_cache_enable(void)
 	}
 #endif
 
-	/* Must disable the L2 before changing the latency parameters */
-	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
 	writel(0x132, &pl310->pl310_tag_latency_ctrl);
 	writel(0x132, &pl310->pl310_data_latency_ctrl);