X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fimx-common%2Fcache.c;h=1c4a9a28c892d1b603f554a85e9cc88c899736a6;hb=4386feb73da7946fc79b55c4fa41c6dd66dcb2e2;hp=54b021cfede98eeb3f74fb66d629a8b5a6f445fa;hpb=ab09e728667563fda9c8a8569331618fcfa0cb16;p=oweals%2Fu-boot.git

diff --git a/arch/arm/imx-common/cache.c b/arch/arm/imx-common/cache.c
index 54b021cfed..1c4a9a28c8 100644
--- a/arch/arm/imx-common/cache.c
+++ b/arch/arm/imx-common/cache.c
@@ -8,6 +8,7 @@
 #include <asm/armv7.h>
 #include <asm/pl310.h>
 #include <asm/io.h>
+#include <asm/imx-common/sys_proto.h>
 
 #ifndef CONFIG_SYS_DCACHE_OFF
 void enable_caches(void)
@@ -39,9 +40,16 @@ void enable_caches(void)
 void v7_outer_cache_enable(void)
 {
 	struct pl310_regs *const pl310 = (struct pl310_regs *)L2_PL310_BASE;
+	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 	unsigned int val;
 
 
+	/*
+	 * Must disable the L2 before changing the latency parameters
+	 * and auxiliary control register.
+	 */
+	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
+
 	/*
 	 * Set bit 22 in the auxiliary control register. If this bit
 	 * is cleared, PL310 treats Normal Shared Non-cacheable
@@ -49,18 +57,14 @@ void v7_outer_cache_enable(void)
 	 */
 	setbits_le32(&pl310->pl310_aux_ctrl, L310_SHARED_ATT_OVERRIDE_ENABLE);
 
-#if defined CONFIG_MX6SL
-	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
-	val = readl(&iomux->gpr[11]);
-	if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
-		/* L2 cache configured as OCRAM, reset it */
-		val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
-		writel(val, &iomux->gpr[11]);
+	if (is_mx6sl() || is_mx6sll()) {
+		val = readl(&iomux->gpr[11]);
+		if (val & IOMUXC_GPR11_L2CACHE_AS_OCRAM) {
+			/* L2 cache configured as OCRAM, reset it */
+			val &= ~IOMUXC_GPR11_L2CACHE_AS_OCRAM;
+			writel(val, &iomux->gpr[11]);
+		}
 	}
-#endif
-
-	/* Must disable the L2 before changing the latency parameters */
-	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
 
 	writel(0x132, &pl310->pl310_tag_latency_ctrl);
 	writel(0x132, &pl310->pl310_data_latency_ctrl);