X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fdts%2Fzynqmp.dtsi;h=aa2815822237e633cb5a4c8a636dde9306725dd4;hb=ba1969028753edc9934323e8fe229c248732e4de;hp=247344fcbb867693c456dd12aa0a76da02dba11a;hpb=b06c46de632c55f4c39d404c6f0f65e414b31050;p=oweals%2Fu-boot.git diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 247344fcbb..aa28158222 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -1,13 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * dts file for Xilinx ZynqMP * - * (C) Copyright 2014 - 2015, Xilinx, Inc. + * (C) Copyright 2014 - 2020, Xilinx, Inc. * * Michal Simek * - * SPDX-License-Identifier: GPL-2.0+ + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. */ +#include +#include + / { compatible = "xlnx,zynqmp"; #address-cells = <2>; @@ -18,7 +25,7 @@ #size-cells = <0>; cpu0: cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; operating-points-v2 = <&cpu_opp_table>; @@ -27,7 +34,7 @@ }; cpu1: cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x1>; @@ -36,7 +43,7 @@ }; cpu2: cpu@2 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x2>; @@ -45,7 +52,7 @@ }; cpu3: cpu@3 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; enable-method = "psci"; reg = <0x3>; @@ -54,7 +61,7 @@ }; idle-states { - entry-method = "arm,psci"; + entry-method = "psci"; CPU_SLEEP_0: cpu-sleep-0 { compatible = "arm,idle-state"; @@ -67,7 +74,7 @@ }; }; - cpu_opp_table: cpu_opp_table { + cpu_opp_table: cpu-opp-table { compatible = "operating-points-v2"; opp-shared; opp00 { @@ -92,159 +99,33 @@ }; }; - dcc: dcc { - compatible = "arm,dcc"; - status = "disabled"; + zynqmp_ipi { u-boot,dm-pre-reloc; - }; - - power-domains { - compatible = "xlnx,zynqmp-genpd"; - - pd_usb0: pd-usb0 { - #power-domain-cells = <0x0>; - pd-id = <0x16>; - }; - - pd_usb1: pd-usb1 { - #power-domain-cells = <0x0>; - pd-id = <0x17>; - }; - - pd_sata: pd-sata { - #power-domain-cells = <0x0>; - pd-id = <0x1c>; - }; - - pd_spi0: pd-spi0 { - #power-domain-cells = <0x0>; - pd-id = <0x23>; - }; - - pd_spi1: pd-spi1 { - #power-domain-cells = <0x0>; - pd-id = <0x24>; - }; - - pd_uart0: pd-uart0 { - #power-domain-cells = <0x0>; - pd-id = <0x21>; - }; - - pd_uart1: pd-uart1 { - #power-domain-cells = <0x0>; - pd-id = <0x22>; - }; - - pd_eth0: pd-eth0 { - #power-domain-cells = <0x0>; - pd-id = <0x1d>; - }; - - pd_eth1: pd-eth1 { - #power-domain-cells = <0x0>; - pd-id = <0x1e>; - }; - - pd_eth2: pd-eth2 { - #power-domain-cells = <0x0>; - pd-id = <0x1f>; - }; - - pd_eth3: pd-eth3 { - #power-domain-cells = <0x0>; - pd-id = <0x20>; - }; - - pd_i2c0: pd-i2c0 { - #power-domain-cells = <0x0>; - pd-id = <0x25>; - }; - - pd_i2c1: pd-i2c1 { - #power-domain-cells = <0x0>; - pd-id = <0x26>; - }; - - pd_dp: pd-dp { - #power-domain-cells = <0x0>; - pd-id = <0x29>; - }; - - pd_gdma: pd-gdma { - #power-domain-cells = <0x0>; - pd-id = <0x2a>; - }; - - pd_adma: pd-adma { - #power-domain-cells = <0x0>; - pd-id = <0x2b>; - }; - - pd_ttc0: pd-ttc0 { - #power-domain-cells = <0x0>; - pd-id = <0x18>; - }; - - pd_ttc1: pd-ttc1 { - #power-domain-cells = <0x0>; - pd-id = <0x19>; - }; - - pd_ttc2: pd-ttc2 { - #power-domain-cells = <0x0>; - pd-id = <0x1a>; - }; - - pd_ttc3: pd-ttc3 { - #power-domain-cells = <0x0>; - pd-id = <0x1b>; - }; - - pd_sd0: pd-sd0 { - #power-domain-cells = <0x0>; - pd-id = <0x27>; - }; - - pd_sd1: pd-sd1 { - #power-domain-cells = <0x0>; - pd-id = <0x28>; - }; - - pd_nand: pd-nand { - #power-domain-cells = <0x0>; - pd-id = <0x2c>; - }; - - pd_qspi: pd-qspi { - #power-domain-cells = <0x0>; - pd-id = <0x2d>; - }; - - pd_gpio: pd-gpio { - #power-domain-cells = <0x0>; - pd-id = <0x2e>; - }; - - pd_can0: pd-can0 { - #power-domain-cells = <0x0>; - pd-id = <0x2f>; - }; - - pd_can1: pd-can1 { - #power-domain-cells = <0x0>; - pd-id = <0x30>; - }; + compatible = "xlnx,zynqmp-ipi-mailbox"; + interrupt-parent = <&gic>; + interrupts = <0 35 4>; + xlnx,ipi-id = <0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; - pd_pcie: pd-pcie { - #power-domain-cells = <0x0>; - pd-id = <0x3b>; + ipi_mailbox_pmu1: mailbox@ff990400 { + u-boot,dm-pre-reloc; + reg = <0x0 0xff9905c0 0x0 0x20>, + <0x0 0xff9905e0 0x0 0x20>, + <0x0 0xff990e80 0x0 0x20>, + <0x0 0xff990ea0 0x0 0x20>; + reg-names = "local_request_region", "local_response_region", + "remote_request_region", "remote_response_region"; + #mbox-cells = <1>; + xlnx,ipi-id = <4>; }; + }; - pd_gpu: pd-gpu { - #power-domain-cells = <0x0>; - pd-id = <0x3a 0x14 0x15>; - }; + dcc: dcc { + compatible = "arm,dcc"; + status = "disabled"; + u-boot,dm-pre-reloc; }; pmu { @@ -262,10 +143,31 @@ }; firmware { - compatible = "xlnx,zynqmp-pm"; - method = "smc"; - interrupt-parent = <&gic>; - interrupts = <0 35 4>; + zynqmp_firmware: zynqmp-firmware { + compatible = "xlnx,zynqmp-firmware"; + method = "smc"; + #power-domain-cells = <0x1>; + u-boot,dm-pre-reloc; + + zynqmp_pcap: pcap { + compatible = "xlnx,zynqmp-pcap-fpga"; + clock-names = "ref_clk"; + }; + + zynqmp_power: zynqmp-power { + u-boot,dm-pre-reloc; + compatible = "xlnx,zynqmp-power"; + interrupt-parent = <&gic>; + interrupts = <0 35 4>; + mboxes = <&ipi_mailbox_pmu1 0>, <&ipi_mailbox_pmu1 1>; + mbox-names = "tx", "rx"; + }; + + zynqmp_reset: reset-controller { + compatible = "xlnx,zynqmp-reset"; + #reset-cells = <1>; + }; + }; }; timer { @@ -283,9 +185,10 @@ fpga_full: fpga-full { compatible = "fpga-region"; - fpga-mgr = <&pcap>; + fpga-mgr = <&zynqmp_pcap>; #address-cells = <2>; #size-cells = <2>; + ranges; }; nvmem_firmware { @@ -298,71 +201,14 @@ }; }; - pcap: pcap { - compatible = "xlnx,zynqmp-pcap-fpga"; - }; - - rst: reset-controller { - compatible = "xlnx,zynqmp-reset"; - #reset-cells = <1>; - }; - - xlnx_dp_snd_card: dp_snd_card { - compatible = "xlnx,dp-snd-card"; - status = "disabled"; - xlnx,dp-snd-pcm = <&xlnx_dp_snd_pcm0>, <&xlnx_dp_snd_pcm1>; - xlnx,dp-snd-codec = <&xlnx_dp_snd_codec0>; - }; - - xlnx_dp_snd_codec0: dp_snd_codec0 { - compatible = "xlnx,dp-snd-codec"; - status = "disabled"; - clock-names = "aud_clk"; - }; - - xlnx_dp_snd_pcm0: dp_snd_pcm0 { - compatible = "xlnx,dp-snd-pcm"; - status = "disabled"; - dmas = <&xlnx_dpdma 4>; - dma-names = "tx"; - }; - - xlnx_dp_snd_pcm1: dp_snd_pcm1 { - compatible = "xlnx,dp-snd-pcm"; - status = "disabled"; - dmas = <&xlnx_dpdma 5>; - dma-names = "tx"; - }; - - xilinx_drm: xilinx_drm { - compatible = "xlnx,drm"; - status = "disabled"; - xlnx,encoder-slave = <&xlnx_dp>; - xlnx,connector-type = "DisplayPort"; - xlnx,dp-sub = <&xlnx_dp_sub>; - planes { - xlnx,pixel-format = "rgb565"; - plane0 { - dmas = <&xlnx_dpdma 3>; - dma-names = "dma0"; - }; - plane1 { - dmas = <&xlnx_dpdma 0>, - <&xlnx_dpdma 1>, - <&xlnx_dpdma 2>; - dma-names = "dma0", "dma1", "dma2"; - }; - }; - }; - - amba_apu: amba_apu@0 { + amba_apu: amba-apu@0 { compatible = "simple-bus"; #address-cells = <2>; #size-cells = <1>; ranges = <0 0 0 0 0xffffffff>; gic: interrupt-controller@f9010000 { - compatible = "arm,gic-400", "arm,cortex-a15-gic"; + compatible = "arm,gic-400"; #interrupt-cells = <3>; reg = <0x0 0xf9010000 0x10000>, <0x0 0xf9020000 0x20000>, @@ -390,7 +236,7 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; - power-domains = <&pd_can0>; + power-domains = <&zynqmp_firmware PD_CAN_0>; }; can1: can@ff070000 { @@ -402,7 +248,7 @@ interrupt-parent = <&gic>; tx-fifo-depth = <0x40>; rx-fifo-depth = <0x40>; - power-domains = <&pd_can1>; + power-domains = <&zynqmp_firmware PD_CAN_1>; }; cci: cci@fd6e0000 { @@ -435,7 +281,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e8>; - power-domains = <&pd_gdma>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan2: dma@fd510000 { @@ -448,7 +294,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14e9>; - power-domains = <&pd_gdma>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan3: dma@fd520000 { @@ -461,7 +307,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ea>; - power-domains = <&pd_gdma>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan4: dma@fd530000 { @@ -474,7 +320,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14eb>; - power-domains = <&pd_gdma>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan5: dma@fd540000 { @@ -487,7 +333,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ec>; - power-domains = <&pd_gdma>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan6: dma@fd550000 { @@ -500,7 +346,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ed>; - power-domains = <&pd_gdma>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan7: dma@fd560000 { @@ -513,7 +359,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ee>; - power-domains = <&pd_gdma>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; fpd_dma_chan8: dma@fd570000 { @@ -526,7 +372,7 @@ xlnx,bus-width = <128>; #stream-id-cells = <1>; iommus = <&smmu 0x14ef>; - power-domains = <&pd_gdma>; + power-domains = <&zynqmp_firmware PD_GDMA>; }; gpu: gpu@fd4b0000 { @@ -537,7 +383,7 @@ interrupts = <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>, <0 132 4>; interrupt-names = "IRQGP", "IRQGPMMU", "IRQPP0", "IRQPPMMU0", "IRQPP1", "IRQPPMMU1"; clock-names = "gpu", "gpu_pp0", "gpu_pp1"; - power-domains = <&pd_gpu>; + power-domains = <&zynqmp_firmware PD_GPU>; }; /* LPDDMA default allows only secured access. inorder to enable @@ -547,105 +393,105 @@ lpd_dma_chan1: dma@ffa80000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa80000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 77 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x868>; - power-domains = <&pd_adma>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan2: dma@ffa90000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffa90000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 78 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x869>; - power-domains = <&pd_adma>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan3: dma@ffaa0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaa0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 79 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86a>; - power-domains = <&pd_adma>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan4: dma@ffab0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffab0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 80 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86b>; - power-domains = <&pd_adma>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan5: dma@ffac0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffac0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 81 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86c>; - power-domains = <&pd_adma>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan6: dma@ffad0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffad0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 82 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86d>; - power-domains = <&pd_adma>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan7: dma@ffae0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffae0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 83 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86e>; - power-domains = <&pd_adma>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; lpd_dma_chan8: dma@ffaf0000 { status = "disabled"; compatible = "xlnx,zynqmp-dma-1.0"; - clock-names = "clk_main", "clk_apb"; reg = <0x0 0xffaf0000 0x0 0x1000>; interrupt-parent = <&gic>; interrupts = <0 84 4>; + clock-names = "clk_main", "clk_apb"; xlnx,bus-width = <64>; #stream-id-cells = <1>; iommus = <&smmu 0x86f>; - power-domains = <&pd_adma>; + power-domains = <&zynqmp_firmware PD_ADMA>; }; mc: memory-controller@fd070000 { @@ -662,15 +508,15 @@ clock-names = "clk_sys", "clk_flash"; interrupt-parent = <&gic>; interrupts = <0 14 4>; - #address-cells = <2>; - #size-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x872>; - power-domains = <&pd_nand>; + power-domains = <&zynqmp_firmware PD_NAND>; }; gem0: ethernet@ff0b0000 { - compatible = "cdns,zynqmp-gem"; + compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 57 4>, <0 57 4>; @@ -680,11 +526,11 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x874>; - power-domains = <&pd_eth0>; + power-domains = <&zynqmp_firmware PD_ETH_0>; }; gem1: ethernet@ff0c0000 { - compatible = "cdns,zynqmp-gem"; + compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 59 4>, <0 59 4>; @@ -694,11 +540,11 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x875>; - power-domains = <&pd_eth1>; + power-domains = <&zynqmp_firmware PD_ETH_1>; }; gem2: ethernet@ff0d0000 { - compatible = "cdns,zynqmp-gem"; + compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 61 4>, <0 61 4>; @@ -708,11 +554,11 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x876>; - power-domains = <&pd_eth2>; + power-domains = <&zynqmp_firmware PD_ETH_2>; }; gem3: ethernet@ff0e0000 { - compatible = "cdns,zynqmp-gem"; + compatible = "cdns,zynqmp-gem", "cdns,gem"; status = "disabled"; interrupt-parent = <&gic>; interrupts = <0 63 4>, <0 63 4>; @@ -722,20 +568,20 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x877>; - power-domains = <&pd_eth3>; + power-domains = <&zynqmp_firmware PD_ETH_3>; }; gpio: gpio@ff0a0000 { compatible = "xlnx,zynqmp-gpio-1.0"; status = "disabled"; #gpio-cells = <0x2>; + gpio-controller; interrupt-parent = <&gic>; interrupts = <0 16 4>; interrupt-controller; #interrupt-cells = <2>; reg = <0x0 0xff0a0000 0x0 0x1000>; - gpio-controller; - power-domains = <&pd_gpio>; + power-domains = <&zynqmp_firmware PD_GPIO>; }; i2c0: i2c@ff020000 { @@ -746,7 +592,7 @@ reg = <0x0 0xff020000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; - power-domains = <&pd_i2c0>; + power-domains = <&zynqmp_firmware PD_I2C_0>; }; i2c1: i2c@ff030000 { @@ -757,7 +603,7 @@ reg = <0x0 0xff030000 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; - power-domains = <&pd_i2c1>; + power-domains = <&zynqmp_firmware PD_I2C_1>; }; ocm: memory-controller@ff960000 { @@ -781,7 +627,8 @@ <0 116 4>, <0 115 4>, /* MSI_1 [63...32] */ <0 114 4>; /* MSI_0 [31...0] */ - interrupt-names = "misc","dummy","intx", "msi1", "msi0"; + interrupt-names = "misc", "dummy", "intx", + "msi1", "msi0"; msi-parent = <&pcie>; reg = <0x0 0xfd0e0000 0x0 0x1000>, <0x0 0xfd480000 0x0 0x1000>, @@ -795,7 +642,7 @@ <0x0 0x0 0x0 0x2 &pcie_intc 0x2>, <0x0 0x0 0x0 0x3 &pcie_intc 0x3>, <0x0 0x0 0x0 0x4 &pcie_intc 0x4>; - power-domains = <&pd_pcie>; + power-domains = <&zynqmp_firmware PD_PCIE>; pcie_intc: legacy-interrupt-controller { interrupt-controller; #address-cells = <0>; @@ -804,6 +651,7 @@ }; qspi: spi@ff0f0000 { + u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-qspi-1.0"; status = "disabled"; clock-names = "ref_clk", "pclk"; @@ -816,7 +664,7 @@ #size-cells = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x873>; - power-domains = <&pd_qspi>; + power-domains = <&zynqmp_firmware PD_QSPI>; }; rtc: rtc@ffa60000 { @@ -838,10 +686,18 @@ reg-names = "serdes", "siou", "lpd"; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; - resets = <&rst 16>, <&rst 59>, <&rst 60>, - <&rst 61>, <&rst 62>, <&rst 63>, - <&rst 64>, <&rst 3>, <&rst 29>, - <&rst 30>, <&rst 31>, <&rst 32>; + resets = <&zynqmp_reset ZYNQMP_RESET_SATA>, + <&zynqmp_reset ZYNQMP_RESET_USB0_CORERESET>, + <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>, + <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, + <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>, + <&zynqmp_reset ZYNQMP_RESET_USB0_APB>, + <&zynqmp_reset ZYNQMP_RESET_USB1_APB>, + <&zynqmp_reset ZYNQMP_RESET_DP>, + <&zynqmp_reset ZYNQMP_RESET_GEM0>, + <&zynqmp_reset ZYNQMP_RESET_GEM1>, + <&zynqmp_reset ZYNQMP_RESET_GEM2>, + <&zynqmp_reset ZYNQMP_RESET_GEM3>; reset-names = "sata_rst", "usb0_crst", "usb1_crst", "usb0_hibrst", "usb1_hibrst", "usb0_apbrst", "usb1_apbrst", "dp_rst", "gem0_rst", @@ -866,14 +722,14 @@ reg = <0x0 0xfd0c0000 0x0 0x2000>; interrupt-parent = <&gic>; interrupts = <0 133 4>; - power-domains = <&pd_sata>; + power-domains = <&zynqmp_firmware PD_SATA>; #stream-id-cells = <4>; iommus = <&smmu 0x4c0>, <&smmu 0x4c1>, <&smmu 0x4c2>, <&smmu 0x4c3>; /* dma-coherent; */ }; - sdhci0: sdhci@ff160000 { + sdhci0: mmc@ff160000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; @@ -884,12 +740,14 @@ xlnx,device_id = <0>; #stream-id-cells = <1>; iommus = <&smmu 0x870>; - power-domains = <&pd_sd0>; + power-domains = <&zynqmp_firmware PD_SD_0>; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; + #clock-cells = <1>; + clock-output-names = "clk_out_sd0", "clk_in_sd0"; }; - sdhci1: sdhci@ff170000 { + sdhci1: mmc@ff170000 { u-boot,dm-pre-reloc; compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; status = "disabled"; @@ -900,9 +758,11 @@ xlnx,device_id = <1>; #stream-id-cells = <1>; iommus = <&smmu 0x871>; - power-domains = <&pd_sd1>; + power-domains = <&zynqmp_firmware PD_SD_1>; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; + #clock-cells = <1>; + clock-output-names = "clk_out_sd1", "clk_in_sd1"; }; pinctrl0: pinctrl@ff180000 { @@ -934,7 +794,7 @@ clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; - power-domains = <&pd_spi0>; + power-domains = <&zynqmp_firmware PD_SPI_0>; }; spi1: spi@ff050000 { @@ -946,7 +806,7 @@ clock-names = "ref_clk", "pclk"; #address-cells = <1>; #size-cells = <0>; - power-domains = <&pd_spi1>; + power-domains = <&zynqmp_firmware PD_SPI_1>; }; ttc0: timer@ff110000 { @@ -956,7 +816,7 @@ interrupts = <0 36 4>, <0 37 4>, <0 38 4>; reg = <0x0 0xff110000 0x0 0x1000>; timer-width = <32>; - power-domains = <&pd_ttc0>; + power-domains = <&zynqmp_firmware PD_TTC_0>; }; ttc1: timer@ff120000 { @@ -966,7 +826,7 @@ interrupts = <0 39 4>, <0 40 4>, <0 41 4>; reg = <0x0 0xff120000 0x0 0x1000>; timer-width = <32>; - power-domains = <&pd_ttc1>; + power-domains = <&zynqmp_firmware PD_TTC_1>; }; ttc2: timer@ff130000 { @@ -976,7 +836,7 @@ interrupts = <0 42 4>, <0 43 4>, <0 44 4>; reg = <0x0 0xff130000 0x0 0x1000>; timer-width = <32>; - power-domains = <&pd_ttc2>; + power-domains = <&zynqmp_firmware PD_TTC_2>; }; ttc3: timer@ff140000 { @@ -986,7 +846,7 @@ interrupts = <0 45 4>, <0 46 4>, <0 47 4>; reg = <0x0 0xff140000 0x0 0x1000>; timer-width = <32>; - power-domains = <&pd_ttc3>; + power-domains = <&zynqmp_firmware PD_TTC_3>; }; uart0: serial@ff000000 { @@ -997,7 +857,7 @@ interrupts = <0 21 4>; reg = <0x0 0xff000000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; - power-domains = <&pd_uart0>; + power-domains = <&zynqmp_firmware PD_UART_0>; }; uart1: serial@ff010000 { @@ -1008,7 +868,7 @@ interrupts = <0 22 4>; reg = <0x0 0xff010000 0x0 0x1000>; clock-names = "uart_clk", "pclk"; - power-domains = <&pd_uart1>; + power-domains = <&zynqmp_firmware PD_UART_1>; }; usb0: usb0@ff9d0000 { @@ -1018,7 +878,7 @@ compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9d0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; - power-domains = <&pd_usb0>; + power-domains = <&zynqmp_firmware PD_USB_0>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; @@ -1044,7 +904,7 @@ compatible = "xlnx,zynqmp-dwc3"; reg = <0x0 0xff9e0000 0x0 0x100>; clock-names = "bus_clk", "ref_clk"; - power-domains = <&pd_usb1>; + power-domains = <&zynqmp_firmware PD_USB_1>; ranges; nvmem-cells = <&soc_revision>; nvmem-cell-names = "soc_revision"; @@ -1069,6 +929,16 @@ interrupt-parent = <&gic>; interrupts = <0 113 1>; reg = <0x0 0xfd4d0000 0x0 0x1000>; + timeout-sec = <60>; + reset-on-timeout; + }; + + lpd_watchdog: watchdog@ff150000 { + compatible = "cdns,wdt-r1p2"; + status = "disabled"; + interrupt-parent = <&gic>; + interrupts = <0 52 1>; + reg = <0x0 0xff150000 0x0 0x1000>; timeout-sec = <10>; }; @@ -1098,39 +968,6 @@ }; }; - xlnx_dp: dp@fd4a0000 { - compatible = "xlnx,v-dp"; - status = "disabled"; - reg = <0x0 0xfd4a0000 0x0 0x1000>; - interrupts = <0 119 4>; - interrupt-parent = <&gic>; - clock-names = "aclk", "aud_clk"; - power-domains = <&pd_dp>; - xlnx,dp-version = "v1.2"; - xlnx,max-lanes = <2>; - xlnx,max-link-rate = <540000>; - xlnx,max-bpc = <16>; - xlnx,enable-ycrcb; - xlnx,colormetry = "rgb"; - xlnx,bpc = <8>; - xlnx,audio-chan = <2>; - xlnx,dp-sub = <&xlnx_dp_sub>; - xlnx,max-pclock-frequency = <300000>; - }; - - xlnx_dp_sub: dp_sub@fd4aa000 { - compatible = "xlnx,dp-sub"; - status = "disabled"; - reg = <0x0 0xfd4aa000 0x0 0x1000>, - <0x0 0xfd4ab000 0x0 0x1000>, - <0x0 0xfd4ac000 0x0 0x1000>; - reg-names = "blend", "av_buf", "aud"; - xlnx,output-fmt = "rgb"; - xlnx,vid-fmt = "yuyv"; - xlnx,gfx-fmt = "rgb565"; - power-domains = <&pd_dp>; - }; - xlnx_dpdma: dma@fd4c0000 { compatible = "xlnx,dpdma"; status = "disabled"; @@ -1138,7 +975,7 @@ interrupts = <0 122 4>; interrupt-parent = <&gic>; clock-names = "axi_clk"; - power-domains = <&pd_dp>; + power-domains = <&zynqmp_firmware PD_DP>; dma-channels = <6>; #dma-cells = <1>; dma-video0channel { @@ -1160,5 +997,62 @@ compatible = "xlnx,audio1"; }; }; + + zynqmp_dpsub: zynqmp-display@fd4a0000 { + compatible = "xlnx,zynqmp-dpsub-1.7"; + status = "disabled"; + reg = <0x0 0xfd4a0000 0x0 0x1000>, + <0x0 0xfd4aa000 0x0 0x1000>, + <0x0 0xfd4ab000 0x0 0x1000>, + <0x0 0xfd4ac000 0x0 0x1000>; + reg-names = "dp", "blend", "av_buf", "aud"; + interrupts = <0 119 4>; + interrupt-parent = <&gic>; + + clock-names = "dp_apb_clk", "dp_aud_clk", + "dp_vtc_pixel_clk_in"; + + power-domains = <&zynqmp_firmware PD_DP>; + + vid-layer { + dma-names = "vid0", "vid1", "vid2"; + dmas = <&xlnx_dpdma 0>, + <&xlnx_dpdma 1>, + <&xlnx_dpdma 2>; + }; + + gfx-layer { + dma-names = "gfx0"; + dmas = <&xlnx_dpdma 3>; + }; + + /* dummy node to indicate there's no child i2c device */ + i2c-bus { + }; + + zynqmp_dp_snd_codec0: zynqmp_dp_snd_codec0 { + compatible = "xlnx,dp-snd-codec"; + clock-names = "aud_clk"; + }; + + zynqmp_dp_snd_pcm0: zynqmp_dp_snd_pcm0 { + compatible = "xlnx,dp-snd-pcm"; + dmas = <&xlnx_dpdma 4>; + dma-names = "tx"; + }; + + zynqmp_dp_snd_pcm1: zynqmp_dp_snd_pcm1 { + compatible = "xlnx,dp-snd-pcm"; + dmas = <&xlnx_dpdma 5>; + dma-names = "tx"; + }; + + zynqmp_dp_snd_card0: zynqmp_dp_snd_card { + compatible = "xlnx,dp-snd-card"; + xlnx,dp-snd-pcm = <&zynqmp_dp_snd_pcm0>, + <&zynqmp_dp_snd_pcm1>; + xlnx,dp-snd-codec = <&zynqmp_dp_snd_codec0>; + }; + }; }; };