X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fdts%2Funiphier-proxstream2.dtsi;h=609cbaa9d7c77cdef6df66168999dec1539554e4;hb=c14d4b0051df5f569fa33d9937af1db267ed6d34;hp=3ba6a4ae51d57b8f0867b3cc2484306d552cf391;hpb=f1993ca066100fcaba7d49fecae0ef604e5807e2;p=oweals%2Fu-boot.git

diff --git a/arch/arm/dts/uniphier-proxstream2.dtsi b/arch/arm/dts/uniphier-proxstream2.dtsi
index 3ba6a4ae51..609cbaa9d7 100644
--- a/arch/arm/dts/uniphier-proxstream2.dtsi
+++ b/arch/arm/dts/uniphier-proxstream2.dtsi
@@ -52,12 +52,6 @@
 			clock-frequency = <50000000>;
 		};
 
-		uart_clk: uart_clk {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <88900000>;
-		};
-
 		i2c_clk: i2c_clk {
 			#clock-cells = <0>;
 			compatible = "fixed-clock";
@@ -78,6 +72,202 @@
 		cache-level = <2>;
 	};
 
+	port0x: gpio@55000008 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000008 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port1x: gpio@55000010 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000010 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port2x: gpio@55000018 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000018 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port3x: gpio@55000020 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000020 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port4: gpio@55000028 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000028 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port5x: gpio@55000030 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000030 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port6x: gpio@55000038 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000038 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port7x: gpio@55000040 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000040 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port8x: gpio@55000048 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000048 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port9x: gpio@55000050 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000050 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port10x: gpio@55000058 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000058 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port12x: gpio@55000068 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000068 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port13x: gpio@55000070 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000070 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port14x: gpio@55000078 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000078 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port15x: gpio@55000080 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000080 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port16x: gpio@55000088 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x55000088 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port17x: gpio@550000a0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000a0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port18x: gpio@550000a8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000a8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port19x: gpio@550000b0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000b0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port20x: gpio@550000b8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000b8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port21x: gpio@550000c0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000c0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port22x: gpio@550000c8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000c8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port23x: gpio@550000d0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000d0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port24x: gpio@550000d8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000d8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port25x: gpio@550000e0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000e0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port26x: gpio@550000e8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000e8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port27x: gpio@550000f0 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000f0 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
+	port28x: gpio@550000f8 {
+		compatible = "socionext,uniphier-gpio";
+		reg = <0x550000f8 0x8>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
+
 	i2c0: i2c@58780000 {
 		compatible = "socionext,uniphier-fi2c";
 		status = "disabled";
@@ -163,6 +353,35 @@
 		clock-frequency = <400000>;
 	};
 
+	emmc: sdhc@5a000000 {
+		compatible = "socionext,uniphier-sdhc";
+		status = "disabled";
+		reg = <0x5a000000 0x800>;
+		interrupts = <0 78 4>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_emmc>;
+		clocks = <&mio_clk 1>;
+		bus-width = <8>;
+		non-removable;
+	};
+
+	sd: sdhc@5a400000 {
+		compatible = "socionext,uniphier-sdhc";
+		status = "disabled";
+		reg = <0x5a400000 0x800>;
+		interrupts = <0 76 4>;
+		pinctrl-names = "default", "1.8v";
+		pinctrl-0 = <&pinctrl_sd>;
+		pinctrl-1 = <&pinctrl_sd_1v8>;
+		clocks = <&mio_clk 0>;
+		bus-width = <4>;
+	};
+
+	aidet@5fc20000 {
+		compatible = "simple-mfd", "syscon";
+		reg = <0x5fc20000 0x200>;
+	};
+
 	usb0: usb@65a00000 {
 		compatible = "socionext,uniphier-xhci", "generic-xhci";
 		status = "disabled";
@@ -182,6 +401,10 @@
 	};
 };
 
+&refclk {
+	clock-frequency = <25000000>;
+};
+
 &serial0 {
 	clock-frequency = <88900000>;
 };
@@ -198,6 +421,30 @@
 	clock-frequency = <88900000>;
 };
 
+&mio_clk {
+	compatible = "socionext,uniphier-pxs2-mio-clock";
+};
+
+&mio_rst {
+	compatible = "socionext,uniphier-pxs2-mio-reset";
+};
+
+&peri_clk {
+	compatible = "socionext,uniphier-pxs2-peri-clock";
+};
+
+&peri_rst {
+	compatible = "socionext,uniphier-pxs2-peri-reset";
+};
+
 &pinctrl {
-	compatible = "socionext,proxstream2-pinctrl", "syscon";
+	compatible = "socionext,uniphier-pxs2-pinctrl";
+};
+
+&sys_clk {
+	compatible = "socionext,uniphier-pxs2-clock";
+};
+
+&sys_rst {
+	compatible = "socionext,uniphier-pxs2-reset";
 };