X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fdts%2Fexynos5420-peach-pit.dts;h=2db4ad2dbd0a98f774c1449a30b96da4cd6cf8ea;hb=c14d4b0051df5f569fa33d9937af1db267ed6d34;hp=5182b2b1c1efb296739ff59b4f89102deae4ae24;hpb=a0942a6d3e08490be2871396c977fb5520ecdf33;p=oweals%2Fu-boot.git

diff --git a/arch/arm/dts/exynos5420-peach-pit.dts b/arch/arm/dts/exynos5420-peach-pit.dts
index 5182b2b1c1..2db4ad2dbd 100644
--- a/arch/arm/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/dts/exynos5420-peach-pit.dts
@@ -9,6 +9,8 @@
 
 /dts-v1/;
 #include "exynos54xx.dtsi"
+#include <dt-bindings/clock/maxim,max77802.h>
+#include <dt-bindings/regulator/maxim,max77802.h>
 
 / {
 	model = "Samsung/Google Peach Pit board based on Exynos5420";
@@ -29,6 +31,14 @@
 		i2c104 = &i2c_tunnel;
 	};
 
+	backlight: backlight {
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 1000000 0>;
+		brightness-levels = <0 100 500 1000 1500 2000 2500 2800>;
+		default-brightness-level = <7>;
+		power-supply = <&tps65090_fet1>;
+	};
+
 	dmc {
 		mem-manuf = "samsung";
 		mem-type = "ddr3";
@@ -65,11 +75,143 @@
 	              compatible = "maxim,max98090-codec";
 	       };
 
-	        edp-lvds-bridge@48 {
-	                compatible = "parade,ps8625";
-	                reg = <0x48>;
-			sleep-gpio = <&gpx3 5 GPIO_ACTIVE_HIGH>;
-			reset-gpio = <&gpy7 7 GPIO_ACTIVE_HIGH>;
+		edp-lvds-bridge@48 {
+			compatible = "parade,ps8625";
+			reg = <0x48>;
+			sleep-gpios = <&gpx3 5 GPIO_ACTIVE_LOW>;
+			reset-gpios = <&gpy7 7 GPIO_ACTIVE_LOW>;
+			parade,regs = /bits/ 8 <
+				0x02 0xa1 0x01  /* HPD low */
+				/*
+				* SW setting
+				* [1:0] SW output 1.2V voltage is lower to 96%
+				*/
+				0x04 0x14 0x01
+				/*
+				* RCO SS setting
+				* [5:4] = b01 0.5%, b10 1%, b11 1.5%
+				*/
+				0x04 0xe3 0x20
+				0x04 0xe2 0x80 /* [7] RCO SS enable */
+				/*
+				*  RPHY Setting
+				* [3:2] CDR tune wait cycle before
+				* measure for fine tune b00: 1us,
+				* 01: 0.5us, 10:2us, 11:4us.
+				*/
+				0x04 0x8a 0x0c
+				0x04 0x89 0x08 /* [3] RFD always on */
+				/*
+				* CTN lock in/out:
+				* 20000ppm/80000ppm. Lock out 2
+				* times.
+				*/
+				0x04 0x71 0x2d
+				/*
+				* 2.7G CDR settings
+				* NOF=40LSB for HBR CDR setting
+				*/
+				0x04 0x7d 0x07
+				0x04 0x7b 0x00  /* [1:0] Fmin=+4bands */
+				0x04 0x7a 0xfd  /* [7:5] DCO_FTRNG=+-40% */
+				/*
+				* 1.62G CDR settings
+				* [5:2]NOF=64LSB [1:0]DCO scale is 2/5
+				*/
+				0x04 0xc0 0x12
+				0x04 0xc1 0x92  /* Gitune=-37% */
+				0x04 0xc2 0x1c  /* Fbstep=100% */
+				0x04 0x32 0x80  /* [7]LOS signal disable */
+				/*
+				* RPIO Setting
+				* [7:4] LVDS driver bias current :
+				* 75% (250mV swing)
+				*/
+				0x04 0x00 0xb0
+				/*
+				* [7:6] Right-bar GPIO output strength is 8mA
+				*/
+				0x04 0x15 0x40
+				/* EQ Training State Machine Setting */
+				0x04 0x54 0x10  /* RCO calibration start */
+				/* [4:0] MAX_LANE_COUNT set to one lane */
+				0x01 0x02 0x81
+				/* [4:0] LANE_COUNT_SET set to one lane */
+				0x01 0x21 0x81
+				0x00 0x52 0x20
+				0x00 0xf1 0x03  /* HPD CP toggle enable */
+				0x00 0x62 0x41
+				/* Counter number add 1ms counter delay */
+				0x00 0xf6 0x01
+				/*
+				* [6]PWM function control by
+				* DPCD0040f[7], default is PWM
+				* block always works.
+				*/
+				0x00 0x77 0x06
+				/*
+				* 04h Adjust VTotal tolerance to
+				* fix the 30Hz no display issue
+				*/
+				0x00 0x4c 0x04
+				/* DPCD00400='h00, Parade OUI = 'h001cf8 */
+				0x01 0xc0 0x00
+				0x01 0xc1 0x1c  /* DPCD00401='h1c */
+				0x01 0xc2 0xf8  /* DPCD00402='hf8 */
+				/*
+				* DPCD403~408 = ASCII code
+				* D2SLV5='h4432534c5635
+				*/
+				0x01 0xc3 0x44
+				0x01 0xc4 0x32  /* DPCD404 */
+				0x01 0xc5 0x53  /* DPCD405 */
+				0x01 0xc6 0x4c  /* DPCD406 */
+				0x01 0xc7 0x56  /* DPCD407 */
+				0x01 0xc8 0x35  /* DPCD408 */
+				/*
+				* DPCD40A, Initial Code major  revision
+				* '01'
+				*/
+				0x01 0xca 0x01
+				/* DPCD40B Initial Code minor revision '05' */
+				0x01 0xcb 0x05
+				/* DPCD720 Select internal PWM */
+				0x01 0xa5 0xa0
+				/*
+				* FFh for 100% PWM of brightness, 0h for 0%
+				* brightness
+				*/
+				0x01 0xa7 0xff
+				/*
+				* Set LVDS output as 6bit-VESA mapping,
+				* single LVDS channel
+				*/
+				0x01 0xcc 0x13
+				/* Enable SSC set by register */
+				0x02 0xb1 0x20
+				/*
+				* Set SSC enabled and +/-1% central
+				* spreading
+				*/
+				0x04 0x10 0x16
+				/* MPU Clock source: LC => RCO */
+				0x04 0x59 0x60
+				0x04 0x54 0x14  /* LC -> RCO */
+				0x02 0xa1 0x91>;  /* HPD high */
+
+			ports {
+				port@0 {
+					bridge_out: endpoint {
+						remote-endpoint = <&panel_in>;
+					};
+				};
+
+				port@1 {
+					bridge_in: endpoint {
+						remote-endpoint = <&dp_out>;
+					};
+				};
+			};
 	        };
 	};
 
@@ -79,9 +221,21 @@
 
 	i2c@12E10000 { /* i2c9 */
 		clock-frequency = <400000>;
-                tpm@20 {
-                        compatible = "infineon,slb9645tt";
-                        reg = <0x20>;
+		tpm@20 {
+			compatible = "infineon,slb9645tt";
+			reg = <0x20>;
+		};
+	};
+
+	panel: panel {
+		compatible = "auo,b116xw03";
+		power-supply = <&tps65090_fet6>;
+		backlight = <&backlight>;
+
+		port {
+			panel_in: endpoint {
+				remote-endpoint = <&bridge_out>;
+			};
 		};
 	};
 
@@ -136,6 +290,25 @@
 	};
 };
 
+&dp {
+	status = "okay";
+	samsung,color-space = <0>;
+	samsung,dynamic-range = <0>;
+	samsung,ycbcr-coeff = <0>;
+	samsung,color-depth = <1>;
+	samsung,link-rate = <0x06>;
+	samsung,lane-count = <2>;
+	samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
+
+	ports {
+		port@0 {
+			dp_out: endpoint {
+				remote-endpoint = <&bridge_in>;
+			};
+		};
+	};
+};
+
 &spi_2 {
 	spi-max-frequency = <3125000>;
 	spi-deactivate-delay = <200>;