X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fdts%2Farmada-8040-mcbin.dts;h=5a046d9de4744468e7ea4779908c05687393c3da;hb=b52fb0b0b5da80a059ba982139401e57ac4e9a2e;hp=e42b092b25085af87975c9227d571fb11161b827;hpb=5cf618ee60a752d058a767372ca1ecb8d9c09b16;p=oweals%2Fu-boot.git

diff --git a/arch/arm/dts/armada-8040-mcbin.dts b/arch/arm/dts/armada-8040-mcbin.dts
index e42b092b25..5a046d9de4 100644
--- a/arch/arm/dts/armada-8040-mcbin.dts
+++ b/arch/arm/dts/armada-8040-mcbin.dts
@@ -1,8 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0
 /*
  * Copyright (C) 2016 Marvell International Ltd.
- *
- * SPDX-License-Identifier:	GPL-2.0
- * https://spdx.org/licenses
  */
 
 #include "armada-8040.dtsi" /* include SoC device tree */
@@ -99,7 +97,7 @@
 	 * [54] 2.5G SFP LOS
 	 * [55] Micro SD card detect
 	 * [56-61] Micro SD
-	 * [62] CP1 KR SFP FAULT
+	 * [62] CP1 SFI SFP FAULT
 	 */
 		/*   0    1    2    3    4    5    6    7    8    9 */
 	pin-func = < 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff
@@ -134,7 +132,7 @@
 	num-lanes = <4>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&cpm_pcie_reset_pins>;
-	marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_HIGH>; /* GPIO[52] */
+	marvell,reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>; /* GPIO[52] */
 	status = "okay";
 };
 
@@ -156,6 +154,12 @@
 	status = "okay";
 };
 
+&cpm_mdio {
+	ge_phy: ethernet-phy@0 {
+		reg = <0>;
+	};
+};
+
 &cpm_comphy {
 	/*
 	 * CP0 Serdes Configuration:
@@ -163,7 +167,7 @@
 	 * Lane 1: PCIe0 (x4)
 	 * Lane 2: PCIe0 (x4)
 	 * Lane 3: PCIe0 (x4)
-	 * Lane 4: KR (10G)
+	 * Lane 4: SFI (10G)
 	 * Lane 5: SATA1
 	 */
 	phy0 {
@@ -179,7 +183,7 @@
 		phy-type = <PHY_TYPE_PEX0>;
 	};
 	phy4 {
-		phy-type = <PHY_TYPE_KR>;
+		phy-type = <PHY_TYPE_SFI>;
 	};
 	phy5 {
 		phy-type = <PHY_TYPE_SATA1>;
@@ -199,6 +203,16 @@
 	status = "okay";
 };
 
+&cps_ethernet {
+	status = "okay";
+};
+
+&cps_eth1 {
+	status = "okay";
+	phy = <&ge_phy>;
+	phy-mode = "sgmii";
+};
+
 &cps_pinctl {
 	/*
 	 * MPP Bus:
@@ -264,15 +278,15 @@
 &cps_comphy {
 	/*
 	 * CP1 Serdes Configuration:
-	 * Lane 0: SGMII2
+	 * Lane 0: SGMII1
 	 * Lane 1: SATA 0
 	 * Lane 2: USB HOST 0
 	 * Lane 3: SATA1
-	 * Lane 4: KR (10G)
+	 * Lane 4: SFI (10G)
 	 * Lane 5: SGMII3
 	 */
 	phy0 {
-		phy-type = <PHY_TYPE_SGMII2>;
+		phy-type = <PHY_TYPE_SGMII1>;
 		phy-speed = <PHY_SPEED_1_25G>;
 	};
 	phy1 {
@@ -285,7 +299,7 @@
 		phy-type = <PHY_TYPE_SATA1>;
 	};
 	phy4 {
-		phy-type = <PHY_TYPE_KR>;
+		phy-type = <PHY_TYPE_SFI>;
 	};
 	phy5 {
 		phy-type = <PHY_TYPE_SGMII3>;