X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv8%2Ffsl-layerscape%2Fsoc.c;h=06f3edb302816345bed5a3f4db54a049dedb0e4a;hb=956520cd7012dfa871bfd06b5f9defd148b4572c;hp=6698c0467d7c0240f2711b14457b2a7088668367;hpb=1c7b5d0309c1da3952b1236d42c82c5ea8446476;p=oweals%2Fu-boot.git diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 6698c0467d..06f3edb302 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -1,19 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright 2014-2015 Freescale Semiconductor - * - * SPDX-License-Identifier: GPL-2.0+ */ #include #include #include -#include -#include #include #include #include #include #include +#include +#include #ifdef CONFIG_LAYERSCAPE_NS_ACCESS #include #endif @@ -25,8 +24,10 @@ #include #endif #include - +#ifdef CONFIG_TFABOOT +#include DECLARE_GLOBAL_DATA_PTR; +#endif bool soc_has_dp_ddr(void) { @@ -66,10 +67,13 @@ static void erratum_a009008(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A009008 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; -#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ + defined(CONFIG_ARCH_LS1012A) set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB1); +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB2); set_usb_txvreftune(scfg, SCFG_USB3PRM1CR_USB3); +#endif #elif defined(CONFIG_ARCH_LS2080A) set_usb_txvreftune(scfg, SCFG_USB3PRM1CR); #endif @@ -87,17 +91,21 @@ static void erratum_a009798(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A009798 u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; -#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ + defined(CONFIG_ARCH_LS1012A) set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB1); +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB2); set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR_USB3); +#endif #elif defined(CONFIG_ARCH_LS2080A) set_usb_sqrxtune(scfg, SCFG_USB3PRM1CR); #endif #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */ } -#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ + defined(CONFIG_ARCH_LS1012A) static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset) { scfg_clrsetbits32(scfg + offset / 4, @@ -109,17 +117,21 @@ static inline void set_usb_pcstxswingfull(u32 __iomem *scfg, u32 offset) static void erratum_a008997(void) { #ifdef CONFIG_SYS_FSL_ERRATUM_A008997 -#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ + defined(CONFIG_ARCH_LS1012A) u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE; set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB1); +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB2); set_usb_pcstxswingfull(scfg, SCFG_USB3PRM2CR_USB3); #endif +#endif #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */ } -#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ + defined(CONFIG_ARCH_LS1012A) #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ @@ -127,7 +139,7 @@ static void erratum_a008997(void) out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3); \ out_be16((phy) + SCFG_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4) -#elif defined(CONFIG_ARCH_LS2080A) +#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) #define PROGRAM_USB_PHY_RX_OVRD_IN_HI(phy) \ out_le16((phy) + DCSR_USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1); \ @@ -139,17 +151,19 @@ static void erratum_a008997(void) static void erratum_a009007(void) { -#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) || \ + defined(CONFIG_ARCH_LS1012A) void __iomem *usb_phy = (void __iomem *)SCFG_USB_PHY1; PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); - +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) usb_phy = (void __iomem *)SCFG_USB_PHY2; PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); usb_phy = (void __iomem *)SCFG_USB_PHY3; PROGRAM_USB_PHY_RX_OVRD_IN_HI(usb_phy); -#elif defined(CONFIG_ARCH_LS2080A) +#endif +#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) void __iomem *dcsr = (void __iomem *)DCSR_BASE; PROGRAM_USB_PHY_RX_OVRD_IN_HI(dcsr + DCSR_USB_PHY1); @@ -260,8 +274,8 @@ static void erratum_rcw_src(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A009203 static void erratum_a009203(void) { - u8 __iomem *ptr; #ifdef CONFIG_SYS_I2C + u8 __iomem *ptr; #ifdef I2C1_BASE_ADDR ptr = (u8 __iomem *)(I2C1_BASE_ADDR + I2C_DEBUG_REG); @@ -297,7 +311,9 @@ void bypass_smmu(void) void fsl_lsch3_early_init_f(void) { erratum_rcw_src(); +#ifdef CONFIG_FSL_IFC init_early_memctl_regs(); /* tighten IFC timing */ +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A009203 erratum_a009203(); #endif @@ -318,46 +334,46 @@ void fsl_lsch3_early_init_f(void) #endif } -#ifdef CONFIG_SCSI_AHCI_PLAT -int sata_init(void) +/* Get VDD in the unit mV from voltage ID */ +int get_core_volt_from_fuse(void) { - struct ccsr_ahci __iomem *ccsr_ahci; - - ccsr_ahci = (void *)CONFIG_SYS_SATA2; - out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); - out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); - out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); - - ccsr_ahci = (void *)CONFIG_SYS_SATA1; - out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); - out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); - out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); + struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + int vdd; + u32 fusesr; + u8 vid; - ahci_init((void __iomem *)CONFIG_SYS_SATA1); - scsi_scan(false); + /* get the voltage ID from fuse status register */ + fusesr = in_le32(&gur->dcfg_fusesr); + debug("%s: fusesr = 0x%x\n", __func__, fusesr); + vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT) & + FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK; + if ((vid == 0) || (vid == FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK)) { + vid = (fusesr >> FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT) & + FSL_CHASSIS3_DCFG_FUSESR_VID_MASK; + } + debug("%s: VID = 0x%x\n", __func__, vid); + switch (vid) { + case 0x00: /* VID isn't supported */ + vdd = -EINVAL; + debug("%s: The VID feature is not supported\n", __func__); + break; + case 0x08: /* 0.9V silicon */ + vdd = 900; + break; + case 0x10: /* 1.0V silicon */ + vdd = 1000; + break; + default: /* Other core voltage */ + vdd = -EINVAL; + debug("%s: The VID(%x) isn't supported\n", __func__, vid); + break; + } + debug("%s: The required minimum volt of CORE is %dmV\n", __func__, vdd); - return 0; + return vdd; } -#endif #elif defined(CONFIG_FSL_LSCH2) -#ifdef CONFIG_SCSI_AHCI_PLAT -int sata_init(void) -{ - struct ccsr_ahci __iomem *ccsr_ahci = (void *)CONFIG_SYS_SATA; - - /* Disable SATA ECC */ - out_le32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + 0x520, 0x80000000); - out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); - out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); - out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); - - ahci_init((void __iomem *)CONFIG_SYS_SATA); - scsi_scan(false); - - return 0; -} -#endif static void erratum_a009929(void) { @@ -456,6 +472,7 @@ static void erratum_a010539(void) porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK; out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), porsr1); + out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff); #endif } @@ -548,6 +565,29 @@ int setup_chip_volt(void) return 0; } +#ifdef CONFIG_FSL_PFE +void init_pfe_scfg_dcfg_regs(void) +{ + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + u32 ecccr2; + + out_be32(&scfg->pfeasbcr, + in_be32(&scfg->pfeasbcr) | SCFG_PFEASBCR_AWCACHE0); + out_be32(&scfg->pfebsbcr, + in_be32(&scfg->pfebsbcr) | SCFG_PFEASBCR_AWCACHE0); + + /* CCI-400 QoS settings for PFE */ + out_be32(&scfg->wr_qos1, (unsigned int)(SCFG_WR_QOS1_PFE1_QOS + | SCFG_WR_QOS1_PFE2_QOS)); + out_be32(&scfg->rd_qos1, (unsigned int)(SCFG_RD_QOS1_PFE1_QOS + | SCFG_RD_QOS1_PFE2_QOS)); + + ecccr2 = in_be32(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2); + out_be32((void *)CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_ECCCR2, + ecccr2 | (unsigned int)DISABLE_PFE_ECC); +} +#endif + void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + @@ -580,6 +620,14 @@ void fsl_lsch2_early_init_f(void) CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN); } + /* + * Program Central Security Unit (CSU) to grant access + * permission for USB 2.0 controller + */ +#if defined(CONFIG_ARCH_LS1012A) && defined(CONFIG_USB_EHCI_FSL) + if (current_el() == 3) + set_devices_ns_access(CSU_CSLX_USB_2, CSU_ALL_RW); +#endif /* Erratum */ erratum_a008850_early(); /* part 1 of 2 */ erratum_a009929(); @@ -589,6 +637,10 @@ void fsl_lsch2_early_init_f(void) erratum_a009798(); erratum_a008997(); erratum_a009007(); + +#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A) + set_icids(); +#endif } #endif @@ -631,15 +683,147 @@ int qspi_ahb_init(void) } #endif +#ifdef CONFIG_TFABOOT +#define MAX_BOOTCMD_SIZE 512 + +int fsl_setenv_bootcmd(void) +{ + int ret; + enum boot_src src = get_boot_src(); + char bootcmd_str[MAX_BOOTCMD_SIZE]; + + switch (src) { +#ifdef IFC_NOR_BOOTCOMMAND + case BOOT_SOURCE_IFC_NOR: + sprintf(bootcmd_str, IFC_NOR_BOOTCOMMAND); + break; +#endif +#ifdef QSPI_NOR_BOOTCOMMAND + case BOOT_SOURCE_QSPI_NOR: + sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND); + break; +#endif +#ifdef XSPI_NOR_BOOTCOMMAND + case BOOT_SOURCE_XSPI_NOR: + sprintf(bootcmd_str, XSPI_NOR_BOOTCOMMAND); + break; +#endif +#ifdef IFC_NAND_BOOTCOMMAND + case BOOT_SOURCE_IFC_NAND: + sprintf(bootcmd_str, IFC_NAND_BOOTCOMMAND); + break; +#endif +#ifdef QSPI_NAND_BOOTCOMMAND + case BOOT_SOURCE_QSPI_NAND: + sprintf(bootcmd_str, QSPI_NAND_BOOTCOMMAND); + break; +#endif +#ifdef XSPI_NAND_BOOTCOMMAND + case BOOT_SOURCE_XSPI_NAND: + sprintf(bootcmd_str, XSPI_NAND_BOOTCOMMAND); + break; +#endif +#ifdef SD_BOOTCOMMAND + case BOOT_SOURCE_SD_MMC: + sprintf(bootcmd_str, SD_BOOTCOMMAND); + break; +#endif +#ifdef SD2_BOOTCOMMAND + case BOOT_SOURCE_SD_MMC2: + sprintf(bootcmd_str, SD2_BOOTCOMMAND); + break; +#endif + default: +#ifdef QSPI_NOR_BOOTCOMMAND + sprintf(bootcmd_str, QSPI_NOR_BOOTCOMMAND); +#endif + break; + } + + ret = env_set("bootcmd", bootcmd_str); + if (ret) { + printf("Failed to set bootcmd: ret = %d\n", ret); + return ret; + } + return 0; +} + +int fsl_setenv_mcinitcmd(void) +{ + int ret = 0; + enum boot_src src = get_boot_src(); + + switch (src) { +#ifdef IFC_MC_INIT_CMD + case BOOT_SOURCE_IFC_NAND: + case BOOT_SOURCE_IFC_NOR: + ret = env_set("mcinitcmd", IFC_MC_INIT_CMD); + break; +#endif +#ifdef QSPI_MC_INIT_CMD + case BOOT_SOURCE_QSPI_NAND: + case BOOT_SOURCE_QSPI_NOR: + ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD); + break; +#endif +#ifdef XSPI_MC_INIT_CMD + case BOOT_SOURCE_XSPI_NAND: + case BOOT_SOURCE_XSPI_NOR: + ret = env_set("mcinitcmd", XSPI_MC_INIT_CMD); + break; +#endif +#ifdef SD_MC_INIT_CMD + case BOOT_SOURCE_SD_MMC: + ret = env_set("mcinitcmd", SD_MC_INIT_CMD); + break; +#endif +#ifdef SD2_MC_INIT_CMD + case BOOT_SOURCE_SD_MMC2: + ret = env_set("mcinitcmd", SD2_MC_INIT_CMD); + break; +#endif + default: +#ifdef QSPI_MC_INIT_CMD + ret = env_set("mcinitcmd", QSPI_MC_INIT_CMD); +#endif + break; + } + + if (ret) { + printf("Failed to set mcinitcmd: ret = %d\n", ret); + return ret; + } + return 0; +} +#endif + #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { -#ifdef CONFIG_SCSI_AHCI_PLAT - sata_init(); -#endif #ifdef CONFIG_CHAIN_OF_TRUST fsl_setenv_chain_of_trust(); #endif +#ifdef CONFIG_TFABOOT + /* + * check if gd->env_addr is default_environment; then setenv bootcmd + * and mcinitcmd. + */ + if (gd->env_addr + gd->reloc_off == (ulong)&default_environment[0]) { + fsl_setenv_bootcmd(); + fsl_setenv_mcinitcmd(); + } + + /* + * If the boot mode is secure, default environment is not present then + * setenv command needs to be run by default + */ +#ifdef CONFIG_CHAIN_OF_TRUST + if ((fsl_check_boot_mode_secure() == 1)) { + fsl_setenv_bootcmd(); + fsl_setenv_mcinitcmd(); + } +#endif +#endif #ifdef CONFIG_QSPI_AHB_INIT qspi_ahb_init(); #endif