X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv7%2Fmx5%2Fclock.c;h=6bef2544564a6e2924ee11426432453f623e0baf;hb=19d829fa60fc4e6df514a046142faaaf9fc8185d;hp=2709860ca274884302c88a895faf00ed97cdb999;hpb=bd23b22badadcdc414a900828253961fc5ec6c39;p=oweals%2Fu-boot.git

diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c
index 2709860ca2..6bef254456 100644
--- a/arch/arm/cpu/armv7/mx5/clock.c
+++ b/arch/arm/cpu/armv7/mx5/clock.c
@@ -4,23 +4,7 @@
  *
  * (C) Copyright 2009 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -101,7 +85,7 @@ void set_usboh3_clk(void)
 			MXC_CCM_CSCDR1_USBOH3_CLK_PODF(1));
 }
 
-void enable_usboh3_clk(unsigned char enable)
+void enable_usboh3_clk(bool enable)
 {
 	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
 
@@ -138,7 +122,7 @@ void set_usb_phy_clk(void)
 }
 
 #if defined(CONFIG_MX51)
-void enable_usb_phy1_clk(unsigned char enable)
+void enable_usb_phy1_clk(bool enable)
 {
 	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
 
@@ -147,12 +131,12 @@ void enable_usb_phy1_clk(unsigned char enable)
 			MXC_CCM_CCGR2_USB_PHY(cg));
 }
 
-void enable_usb_phy2_clk(unsigned char enable)
+void enable_usb_phy2_clk(bool enable)
 {
 	/* i.MX51 has a single USB PHY clock, so do nothing here. */
 }
 #elif defined(CONFIG_MX53)
-void enable_usb_phy1_clk(unsigned char enable)
+void enable_usb_phy1_clk(bool enable)
 {
 	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
 
@@ -161,7 +145,7 @@ void enable_usb_phy1_clk(unsigned char enable)
 			MXC_CCM_CCGR4_USB_PHY1(cg));
 }
 
-void enable_usb_phy2_clk(unsigned char enable)
+void enable_usb_phy2_clk(bool enable)
 {
 	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
 
@@ -338,7 +322,7 @@ static u32 get_ipg_per_clk(void)
 /* Get the output clock rate of a standard PLL MUX for peripherals. */
 static u32 get_standard_pll_sel_clk(u32 clk_sel)
 {
-	u32 freq;
+	u32 freq = 0;
 
 	switch (clk_sel & 0x3) {
 	case 0:
@@ -739,10 +723,11 @@ static int config_core_clk(u32 ref, u32 freq)
 static int config_nfc_clk(u32 nfc_clk)
 {
 	u32 parent_rate = get_emi_slow_clk();
-	u32 div = parent_rate / nfc_clk;
+	u32 div;
 
-	if (nfc_clk <= 0)
+	if (nfc_clk == 0)
 		return -EINVAL;
+	div = parent_rate / nfc_clk;
 	if (div == 0)
 		div++;
 	if (parent_rate / div > NFC_CLK_MAX)
@@ -755,6 +740,15 @@ static int config_nfc_clk(u32 nfc_clk)
 	return 0;
 }
 
+void enable_nfc_clk(unsigned char enable)
+{
+	unsigned int cg = enable ? MXC_CCM_CCGR_CG_ON : MXC_CCM_CCGR_CG_OFF;
+
+	clrsetbits_le32(&mxc_ccm->CCGR5,
+		MXC_CCM_CCGR5_EMI_ENFC(MXC_CCM_CCGR_CG_MASK),
+		MXC_CCM_CCGR5_EMI_ENFC(cg));
+}
+
 /* Config main_bus_clock for periphs */
 static int config_periph_clk(u32 ref, u32 freq)
 {
@@ -928,7 +922,9 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 	printf("IPG        %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000);
 	printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000);
 	printf("DDR        %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000);
-
+#ifdef CONFIG_MXC_SPI
+	printf("CSPI       %8d kHz\n", mxc_get_clock(MXC_CSPI_CLK) / 1000);
+#endif
 	return 0;
 }