X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farmv7%2Fam33xx%2Fclock_am43xx.c;h=5c2a2ab0f28d785e0b8e71756c80980336f005a5;hb=7b77b1f63bd0fb2640a445b7f677b366b0616889;hp=fb654bb836f136b19b146e0c7575ccd190f432bf;hpb=4c89a369c7cd6e7ad3adec4601cfa69fec476164;p=oweals%2Fu-boot.git

diff --git a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
index fb654bb836..5c2a2ab0f2 100644
--- a/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
+++ b/arch/arm/cpu/armv7/am33xx/clock_am43xx.c
@@ -53,6 +53,8 @@ const struct dpll_regs dpll_ddr_regs = {
 
 void setup_clocks_for_console(void)
 {
+	u32 clkctrl, idlest = MODULE_CLKCTRL_IDLEST_DISABLED;
+
 	/* Do not add any spl_debug prints in this function */
 	clrsetbits_le32(&cmwkup->wkclkstctrl, CD_CLKCTRL_CLKTRCTRL_MASK,
 			CD_CLKCTRL_CLKTRCTRL_SW_WKUP <<
@@ -63,6 +65,13 @@ void setup_clocks_for_console(void)
 			MODULE_CLKCTRL_MODULEMODE_MASK,
 			MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN <<
 			MODULE_CLKCTRL_MODULEMODE_SHIFT);
+
+	while ((idlest == MODULE_CLKCTRL_IDLEST_DISABLED) ||
+		(idlest == MODULE_CLKCTRL_IDLEST_TRANSITIONING)) {
+		clkctrl = readl(&cmwkup->wkup_uart0ctrl);
+		idlest = (clkctrl & MODULE_CLKCTRL_IDLEST_MASK) >>
+			 MODULE_CLKCTRL_IDLEST_SHIFT;
+	}
 }
 
 void enable_basic_clocks(void)
@@ -94,11 +103,15 @@ void enable_basic_clocks(void)
 		&cmper->gpio1clkctrl,
 		&cmper->gpio2clkctrl,
 		&cmper->gpio3clkctrl,
+		&cmper->gpio4clkctrl,
+		&cmper->gpio5clkctrl,
 		&cmper->i2c1clkctrl,
+		&cmper->cpgmac0clkctrl,
 		&cmper->emiffwclkctrl,
 		&cmper->emifclkctrl,
 		&cmper->otfaemifclkctrl,
 		&cmper->qspiclkctrl,
+		&cmper->spi0clkctrl,
 		0
 	};
 
@@ -106,4 +119,113 @@ void enable_basic_clocks(void)
 
 	/* Select the Master osc clk as Timer2 clock source */
 	writel(0x1, &cmdpll->clktimer2clk);
+
+	/* For OPP100 the mac clock should be /5. */
+	writel(0x4, &cmdpll->clkselmacclk);
+}
+
+#ifdef CONFIG_TI_EDMA3
+void enable_edma3_clocks(void)
+{
+	u32 *const clk_domains_edma3[] = {
+		0
+	};
+
+	u32 *const clk_modules_explicit_en_edma3[] = {
+		&cmper->tpccclkctrl,
+		&cmper->tptc0clkctrl,
+		0
+	};
+
+	do_enable_clocks(clk_domains_edma3,
+			 clk_modules_explicit_en_edma3,
+			 1);
+}
+
+void disable_edma3_clocks(void)
+{
+	u32 *const clk_domains_edma3[] = {
+		0
+	};
+
+	u32 *const clk_modules_disable_edma3[] = {
+		&cmper->tpccclkctrl,
+		&cmper->tptc0clkctrl,
+		0
+	};
+
+	do_disable_clocks(clk_domains_edma3,
+			  clk_modules_disable_edma3,
+			  1);
+}
+#endif
+
+#ifdef CONFIG_USB_DWC3
+void enable_usb_clocks(int index)
+{
+	u32 *usbclkctrl = 0;
+	u32 *usbphyocp2scpclkctrl = 0;
+
+	if (index == 0) {
+		usbclkctrl = &cmper->usb0clkctrl;
+		usbphyocp2scpclkctrl = &cmper->usbphyocp2scp0clkctrl;
+		setbits_le32(&cmper->usb0clkctrl,
+			     USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
+		setbits_le32(&cmwkup->usbphy0clkctrl,
+			     USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
+	} else if (index == 1) {
+		usbclkctrl = &cmper->usb1clkctrl;
+		usbphyocp2scpclkctrl = &cmper->usbphyocp2scp1clkctrl;
+		setbits_le32(&cmper->usb1clkctrl,
+			     USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
+		setbits_le32(&cmwkup->usbphy1clkctrl,
+			     USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
+	}
+
+	u32 *const clk_domains_usb[] = {
+		0
+	};
+
+	u32 *const clk_modules_explicit_en_usb[] = {
+		usbclkctrl,
+		usbphyocp2scpclkctrl,
+		0
+	};
+
+	do_enable_clocks(clk_domains_usb, clk_modules_explicit_en_usb, 1);
+}
+
+void disable_usb_clocks(int index)
+{
+	u32 *usbclkctrl = 0;
+	u32 *usbphyocp2scpclkctrl = 0;
+
+	if (index == 0) {
+		usbclkctrl = &cmper->usb0clkctrl;
+		usbphyocp2scpclkctrl = &cmper->usbphyocp2scp0clkctrl;
+		clrbits_le32(&cmper->usb0clkctrl,
+			     USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
+		clrbits_le32(&cmwkup->usbphy0clkctrl,
+			     USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
+	} else if (index == 1) {
+		usbclkctrl = &cmper->usb1clkctrl;
+		usbphyocp2scpclkctrl = &cmper->usbphyocp2scp1clkctrl;
+		clrbits_le32(&cmper->usb1clkctrl,
+			     USBOTGSSX_CLKCTRL_OPTFCLKEN_REFCLK960);
+		clrbits_le32(&cmwkup->usbphy1clkctrl,
+			     USBPHY0_CLKCTRL_OPTFCLKEN_CLK32K);
+	}
+
+	u32 *const clk_domains_usb[] = {
+		0
+	};
+
+	u32 *const clk_modules_disable_usb[] = {
+		usbclkctrl,
+		usbphyocp2scpclkctrl,
+		0
+	};
+
+	do_disable_clocks(clk_domains_usb, clk_modules_disable_usb, 1);
 }
+#endif