X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=arch%2Farm%2Fcpu%2Farm926ejs%2Fmx25%2Fgeneric.c;h=8b07dae2b938a6cbc8021291c22f27f70e0bd4c1;hb=42d25327f596772b75ae42951f5909d0a66c67e3;hp=694841dd10eed1bf51b67099fe6bff35a1b41479;hpb=83653121d7382fccfe329cb732f77f116341ef1d;p=oweals%2Fu-boot.git

diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c
index 694841dd10..8b07dae2b9 100644
--- a/arch/arm/cpu/arm926ejs/mx25/generic.c
+++ b/arch/arm/cpu/arm926ejs/mx25/generic.c
@@ -28,10 +28,15 @@
 #include <asm/io.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/imx25-pinmux.h>
+#include <asm/arch/clock.h>
 #ifdef CONFIG_MXC_MMC
 #include <asm/arch/mxcmmc.h>
 #endif
 
+#ifdef CONFIG_FSL_ESDHC
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
 /*
  *  get the system pll clock in Hz
  *
@@ -39,7 +44,7 @@
  *  f = 2 * f_ref * --------------------
  *                        pd + 1
  */
-static unsigned int imx_decode_pll (unsigned int pll, unsigned int f_ref)
+static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
 {
 	unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
 	    & CCM_PLL_MFI_MASK;
@@ -52,100 +57,173 @@ static unsigned int imx_decode_pll (unsigned int pll, unsigned int f_ref)
 
 	mfi = mfi <= 5 ? 5 : mfi;
 
-	return lldiv (2 * (u64) f_ref * (mfi * (mfd + 1) + mfn),
+	return lldiv(2 * (u64) f_ref * (mfi * (mfd + 1) + mfn),
 		      (mfd + 1) * (pd + 1));
 }
 
-static ulong imx_get_mpllclk (void)
+static ulong imx_get_mpllclk(void)
 {
 	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
 	ulong fref = 24000000;
 
-	return imx_decode_pll (readl (&ccm->mpctl), fref);
+	return imx_decode_pll(readl(&ccm->mpctl), fref);
 }
 
-ulong imx_get_armclk (void)
+ulong imx_get_armclk(void)
 {
 	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong cctl = readl (&ccm->cctl);
-	ulong fref = imx_get_mpllclk ();
+	ulong cctl = readl(&ccm->cctl);
+	ulong fref = imx_get_mpllclk();
 	ulong div;
 
 	if (cctl & CCM_CCTL_ARM_SRC)
-		fref = lldiv ((fref * 3), 4);
+		fref = lldiv((fref * 3), 4);
 
 	div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
 	       & CCM_CCTL_ARM_DIV_MASK) + 1;
 
-	return lldiv (fref, div);
+	return lldiv(fref, div);
 }
 
-ulong imx_get_ahbclk (void)
+ulong imx_get_ahbclk(void)
 {
 	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong cctl = readl (&ccm->cctl);
-	ulong fref = imx_get_armclk ();
+	ulong cctl = readl(&ccm->cctl);
+	ulong fref = imx_get_armclk();
 	ulong div;
 
 	div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
 	       & CCM_CCTL_AHB_DIV_MASK) + 1;
 
-	return lldiv (fref, div);
+	return lldiv(fref, div);
 }
 
-ulong imx_get_perclk (int clk)
+ulong imx_get_perclk(int clk)
 {
 	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
-	ulong fref = imx_get_ahbclk ();
+	ulong fref = imx_get_ahbclk();
 	ulong div;
 
-	div = readl (&ccm->pcdr[CCM_PERCLK_REG (clk)]);
-	div = ((div >> CCM_PERCLK_SHIFT (clk)) & CCM_PERCLK_MASK) + 1;
+	div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
+	div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
+
+	return lldiv(fref, div);
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+	if (clk >= MXC_CLK_NUM)
+		return -1;
+	switch (clk) {
+	case MXC_ARM_CLK:
+		return imx_get_armclk();
+	case MXC_FEC_CLK:
+		return imx_get_ahbclk();
+	default:
+		return imx_get_perclk(clk);
+	}
+}
 
-	return lldiv (fref, div);
+u32 get_cpu_rev(void)
+{
+	u32 srev;
+	u32 system_rev = 0x25000;
+
+	/* read SREV register from IIM module */
+	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+	srev = readl(&iim->iim_srev);
+
+	switch (srev) {
+	case 0x00:
+		system_rev |= CHIP_REV_1_0;
+		break;
+	case 0x01:
+		system_rev |= CHIP_REV_1_1;
+		break;
+	default:
+		system_rev |= 0x8000;
+		break;
+	}
+
+	return system_rev;
 }
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
-int print_cpuinfo (void)
+static char *get_reset_cause(void)
+{
+	/* read RCSR register from CCM module */
+	struct ccm_regs *ccm =
+		(struct ccm_regs *)IMX_CCM_BASE;
+
+	u32 cause = readl(&ccm->rcsr) & 0x0f;
+
+	if (cause == 0)
+		return "POR";
+	else if (cause == 1)
+		return "RST";
+	else if ((cause & 2) == 2)
+		return "WDOG";
+	else if ((cause & 4) == 4)
+		return "SW RESET";
+	else if ((cause & 8) == 8)
+		return "JTAG";
+	else
+		return "unknown reset";
+
+}
+
+int print_cpuinfo(void)
 {
 	char buf[32];
+	u32 cpurev = get_cpu_rev();
 
-	printf ("CPU:   Freescale i.MX25 at %s MHz\n\n",
-		strmhz (buf, imx_get_mpllclk ()));
+	printf("CPU:   Freescale i.MX25 rev%d.%d%s at %s MHz\n",
+		(cpurev & 0xF0) >> 4, (cpurev & 0x0F),
+		((cpurev & 0x8000) ? " unknown" : ""),
+		strmhz(buf, imx_get_armclk()));
+	printf("Reset cause: %s\n\n", get_reset_cause());
 	return 0;
 }
 #endif
 
-int cpu_eth_init (bd_t * bis)
+int cpu_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_FEC_MXC)
 	struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
 	ulong val;
 
-	val = readl (&ccm->cgr0);
+	val = readl(&ccm->cgr0);
 	val |= (1 << 23);
-	writel (val, &ccm->cgr0);
-	return fecmxc_initialize (bis);
+	writel(val, &ccm->cgr0);
+	return fecmxc_initialize(bis);
 #else
 	return 0;
 #endif
 }
 
+int get_clocks(void)
+{
+#ifdef CONFIG_FSL_ESDHC
+	gd->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
+#endif
+	return 0;
+}
+
 /*
  * Initializes on-chip MMC controllers.
  * to override, implement board_mmc_init()
  */
-int cpu_mmc_init (bd_t * bis)
+int cpu_mmc_init(bd_t *bis)
 {
 #ifdef CONFIG_MXC_MMC
-	return mxc_mmc_init (bis);
+	return mxc_mmc_init(bis);
 #else
 	return 0;
 #endif
 }
 
 #ifdef CONFIG_MXC_UART
-void mx25_uart_init_pins (void)
+void mx25_uart1_init_pins(void)
 {
 	struct iomuxc_mux_ctl *muxctl;
 	struct iomuxc_pad_ctl *padctl;
@@ -155,7 +233,7 @@ void mx25_uart_init_pins (void)
 
 	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
 	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
-	muxmode0 = MX25_PIN_MUX_MODE (0);
+	muxmode0 = MX25_PIN_MUX_MODE(0);
 	/*
 	 * set up input pins with hysteresis and 100K pull-ups
 	 */
@@ -176,25 +254,25 @@ void mx25_uart_init_pins (void)
 
 	/* UART1 */
 	/* rxd */
-	writel (muxmode0, &muxctl->pad_uart1_rxd);
-	writel (inpadctl, &padctl->pad_uart1_rxd);
+	writel(muxmode0, &muxctl->pad_uart1_rxd);
+	writel(inpadctl, &padctl->pad_uart1_rxd);
 
 	/* txd */
-	writel (muxmode0, &muxctl->pad_uart1_txd);
-	writel (outpadctl, &padctl->pad_uart1_txd);
+	writel(muxmode0, &muxctl->pad_uart1_txd);
+	writel(outpadctl, &padctl->pad_uart1_txd);
 
 	/* rts */
-	writel (muxmode0, &muxctl->pad_uart1_rts);
-	writel (outpadctl, &padctl->pad_uart1_rts);
+	writel(muxmode0, &muxctl->pad_uart1_rts);
+	writel(outpadctl, &padctl->pad_uart1_rts);
 
 	/* cts */
-	writel (muxmode0, &muxctl->pad_uart1_cts);
-	writel (inpadctl, &padctl->pad_uart1_cts);
+	writel(muxmode0, &muxctl->pad_uart1_cts);
+	writel(inpadctl, &padctl->pad_uart1_cts);
 }
 #endif /* CONFIG_MXC_UART */
 
 #ifdef CONFIG_FEC_MXC
-void mx25_fec_init_pins (void)
+void mx25_fec_init_pins(void)
 {
 	struct iomuxc_mux_ctl *muxctl;
 	struct iomuxc_pad_ctl *padctl;
@@ -205,7 +283,7 @@ void mx25_fec_init_pins (void)
 
 	muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE;
 	padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE;
-	muxmode0 = MX25_PIN_MUX_MODE (0);
+	muxmode0 = MX25_PIN_MUX_MODE(0);
 	inpadctl_100kpd = MX25_PIN_PAD_CTL_HYS
 	    | MX25_PIN_PAD_CTL_PKE
 	    | MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
@@ -224,40 +302,52 @@ void mx25_fec_init_pins (void)
 	outpadctl = MX25_PIN_PAD_CTL_PUE | MX25_PIN_PAD_CTL_100K_PD;
 
 	/* FEC_TX_CLK */
-	writel (muxmode0, &muxctl->pad_fec_tx_clk);
-	writel (inpadctl_100kpd, &padctl->pad_fec_tx_clk);
+	writel(muxmode0, &muxctl->pad_fec_tx_clk);
+	writel(inpadctl_100kpd, &padctl->pad_fec_tx_clk);
 
 	/* FEC_RX_DV */
-	writel (muxmode0, &muxctl->pad_fec_rx_dv);
-	writel (inpadctl_100kpd, &padctl->pad_fec_rx_dv);
+	writel(muxmode0, &muxctl->pad_fec_rx_dv);
+	writel(inpadctl_100kpd, &padctl->pad_fec_rx_dv);
 
 	/* FEC_RDATA0 */
-	writel (muxmode0, &muxctl->pad_fec_rdata0);
-	writel (inpadctl_100kpd, &padctl->pad_fec_rdata0);
+	writel(muxmode0, &muxctl->pad_fec_rdata0);
+	writel(inpadctl_100kpd, &padctl->pad_fec_rdata0);
 
 	/* FEC_TDATA0 */
-	writel (muxmode0, &muxctl->pad_fec_tdata0);
-	writel (outpadctl, &padctl->pad_fec_tdata0);
+	writel(muxmode0, &muxctl->pad_fec_tdata0);
+	writel(outpadctl, &padctl->pad_fec_tdata0);
 
 	/* FEC_TX_EN */
-	writel (muxmode0, &muxctl->pad_fec_tx_en);
-	writel (outpadctl, &padctl->pad_fec_tx_en);
+	writel(muxmode0, &muxctl->pad_fec_tx_en);
+	writel(outpadctl, &padctl->pad_fec_tx_en);
 
 	/* FEC_MDC */
-	writel (muxmode0, &muxctl->pad_fec_mdc);
-	writel (outpadctl, &padctl->pad_fec_mdc);
+	writel(muxmode0, &muxctl->pad_fec_mdc);
+	writel(outpadctl, &padctl->pad_fec_mdc);
 
 	/* FEC_MDIO */
-	writel (muxmode0, &muxctl->pad_fec_mdio);
-	writel (inpadctl_22kpu, &padctl->pad_fec_mdio);
+	writel(muxmode0, &muxctl->pad_fec_mdio);
+	writel(inpadctl_22kpu, &padctl->pad_fec_mdio);
 
 	/* FEC_RDATA1 */
-	writel (muxmode0, &muxctl->pad_fec_rdata1);
-	writel (inpadctl_100kpd, &padctl->pad_fec_rdata1);
+	writel(muxmode0, &muxctl->pad_fec_rdata1);
+	writel(inpadctl_100kpd, &padctl->pad_fec_rdata1);
 
 	/* FEC_TDATA1 */
-	writel (muxmode0, &muxctl->pad_fec_tdata1);
-	writel (outpadctl, &padctl->pad_fec_tdata1);
+	writel(muxmode0, &muxctl->pad_fec_tdata1);
+	writel(outpadctl, &padctl->pad_fec_tdata1);
 
 }
+
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+	int i;
+	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+	struct fuse_bank *bank = &iim->bank[0];
+	struct fuse_bank0_regs *fuse =
+			(struct fuse_bank0_regs *)bank->fuse_regs;
+
+	for (i = 0; i < 6; i++)
+		mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
+}
 #endif /* CONFIG_FEC_MXC */