X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=README;h=bd035235c129c61b14811a8c8b8c81932a1b2acf;hb=80528a7848773c304c95751d96388fd2af939189;hp=99320abadd8e94f131077d7efd2b34e55a4e67b6;hpb=8d321b81c5441db93425ee37cb79cc51d9ce2fb0;p=oweals%2Fu-boot.git diff --git a/README b/README index 99320abadd..bd035235c1 100644 --- a/README +++ b/README @@ -126,13 +126,17 @@ the string "u_boot" or on "U_BOOT". Example: Versioning: =========== -U-Boot uses a 3 level version number containing a version, a -sub-version, and a patchlevel: "U-Boot-2.34.5" means version "2", -sub-version "34", and patchlevel "4". +Starting with the release in October 2008, the names of the releases +were changed from numerical release numbers without deeper meaning +into a time stamp based numbering. Regular releases are identified by +names consisting of the calendar year and month of the release date. +Additional fields (if present) indicate release candidates or bug fix +releases in "stable" maintenance trees. -The patchlevel is used to indicate certain stages of development -between released versions, i. e. officially released versions of -U-Boot will always have a patchlevel of "0". +Examples: + U-Boot v2009.11 - Release November 2009 + U-Boot v2009.11.1 - Release 1 in version November 2009 stable tree + U-Boot v2010.09-rc1 - Release candiate 1 for September 2010 release Directory Hierarchy: @@ -143,9 +147,9 @@ Directory Hierarchy: /cpu CPU specific files /arm720t Files specific to ARM 720 CPUs /arm920t Files specific to ARM 920 CPUs - /at91rm9200 Files specific to Atmel AT91RM9200 CPU - /imx Files specific to Freescale MC9328 i.MX CPUs - /s3c24x0 Files specific to Samsung S3C24X0 CPUs + /at91rm9200 Files specific to Atmel AT91RM9200 CPU + /imx Files specific to Freescale MC9328 i.MX CPUs + /s3c24x0 Files specific to Samsung S3C24X0 CPUs /arm925t Files specific to ARM 925 CPUs /arm926ejs Files specific to ARM 926 CPUs /arm1136 Files specific to ARM 1136 CPUs @@ -177,13 +181,10 @@ Directory Hierarchy: /mips Files generic to MIPS architecture /cpu CPU specific files /lib Architecture specific library files - /nios Files generic to Altera NIOS architecture - /cpu CPU specific files - /lib Architecture specific library files /nios2 Files generic to Altera NIOS2 architecture /cpu CPU specific files /lib Architecture specific library files - /ppc Files generic to PowerPC architecture + /powerpc Files generic to PowerPC architecture /cpu CPU specific files /74xx_7xx Files specific to Freescale MPC74xx and 7xx CPUs /mpc5xx Files specific to Freescale MPC5xx CPUs @@ -318,6 +319,11 @@ The following options need to be configured: CONFIG_SYS_PQ2FADS - PQ2FADS-ZU or PQ2FADS-VR CONFIG_SYS_8272ADS - MPC8272ADS +- Marvell Family Member + CONFIG_SYS_MVFS - define it if you want to enable + multiple fs option at one time + for marvell soc family + - MPC824X Family Member (if CONFIG_MPC824X is defined) Define exactly one of CONFIG_MPC8240, CONFIG_MPC8245 @@ -535,25 +541,6 @@ The following options need to be configured: must be defined, to setup the maximum idle timeout for the SMC. -- Interrupt driven serial port input: - CONFIG_SERIAL_SOFTWARE_FIFO - - PPC405GP only. - Use an interrupt handler for receiving data on the - serial port. It also enables using hardware handshake - (RTS/CTS) and UART's built-in FIFO. Set the number of - bytes the interrupt driven input buffer should have. - - Leave undefined to disable this feature, including - disable the buffer and hardware handshake. - -- Console UART Number: - CONFIG_UART1_CONSOLE - - AMCC PPC4xx only. - If defined internal UART1 (and not UART0) is used - as default U-Boot console. - - Boot Delay: CONFIG_BOOTDELAY - in seconds Delay before automatically booting the default image; set to -1 to disable autoboot. @@ -693,7 +680,7 @@ The following options need to be configured: (requires CONFIG_CMD_I2C) CONFIG_CMD_SETGETDCR Support for DCR Register access (4xx only) - CONFIG_CMD_SHA1 print sha1 memory digest + CONFIG_CMD_SHA1SUM print sha1 memory digest (requires CONFIG_CMD_MEMORY) CONFIG_CMD_SOURCE "source" command Support CONFIG_CMD_SPI * SPI serial bus support @@ -764,6 +751,10 @@ The following options need to be configured: CONFIG_PCA953X - use NXP's PCA953X series I2C GPIO CONFIG_PCA953X_INFO - enable pca953x info command + The CONFIG_SYS_I2C_PCA953X_WIDTH option specifies a list of + chip-ngpio pairs that tell the PCA953X driver the number of + pins supported by a particular chip. + Note that if the GPIO device uses I2C, then the I2C interface must also be configured. See I2C Support, below. @@ -879,6 +870,18 @@ The following options need to be configured: Define this to use i/o functions instead of macros (some hardware wont work with macros) + CONFIG_FTGMAC100 + Support for Faraday's FTGMAC100 Gigabit SoC Ethernet + + CONFIG_FTGMAC100_EGIGA + Define this to use GE link update with gigabit PHY. + Define this if FTGMAC100 is connected to gigabit PHY. + If your system has 10/100 PHY only, it might not occur + wrong behavior. Because PHY usually return timeout or + useless data when polling gigabit status and gigabit + control registers. This behavior won't affect the + correctnessof 10/100 link speed update. + CONFIG_SMC911X Support for SMSC's LAN911x and LAN921x chips @@ -894,6 +897,18 @@ The following options need to be configured: automatically converts one 32 bit word to two 16 bit words you may also try CONFIG_SMC911X_32_BIT. + CONFIG_SH_ETHER + Support for Renesas on-chip Ethernet controller + + CONFIG_SH_ETHER_USE_PORT + Define the number of ports to be used + + CONFIG_SH_ETHER_PHY_ADDR + Define the ETH PHY's address + + CONFIG_SH_ETHER_CACHE_WRITEBACK + If this option is set, the driver enables cache flush. + - USB Support: At the moment only the UHCI host controller is supported (PIP405, MIP405, MPC5200); define @@ -1059,6 +1074,28 @@ The following options need to be configured: and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP or CONFIG_VIDEO_SED13806_16BPP + CONFIG_FSL_DIU_FB + Enable the Freescale DIU video driver. Reference boards for + SOCs that have a DIU should define this macro to enable DIU + support, and should also define these other macros: + + CONFIG_SYS_DIU_ADDR + CONFIG_VIDEO + CONFIG_CMD_BMP + CONFIG_CFB_CONSOLE + CONFIG_VIDEO_SW_CURSOR + CONFIG_VGA_AS_SINGLE_DEVICE + CONFIG_VIDEO_LOGO + CONFIG_VIDEO_BMP_LOGO + + The DIU driver will look for the 'monitor' environment variable, + and if defined, enable the DIU as a console during boot. This + variable should be set to one of these values: + + '0' Output video to the DVI connector + '1' Output video to the LVDS connector + '2' Output video to the Dual-Link LVDS connector + - Keyboard Support: CONFIG_KEYBOARD @@ -1417,7 +1454,7 @@ The following options need to be configured: the CPU's i2c node address). Now, the u-boot i2c code for the mpc8xx - (arch/ppc/cpu/mpc8xx/i2c.c) sets the CPU up as a master node + (arch/powerpc/cpu/mpc8xx/i2c.c) sets the CPU up as a master node and so its address should therefore be cleared to 0 (See, eg, MPC823e User's Manual p.16-473). So, set CONFIG_SYS_I2C_SLAVE to 0. @@ -1498,6 +1535,16 @@ The following options need to be configured: #define I2C_DELAY udelay(2) + CONFIG_SOFT_I2C_GPIO_SCL / CONFIG_SOFT_I2C_GPIO_SDA + + If your arch supports the generic GPIO framework (asm/gpio.h), + then you may alternatively define the two GPIOs that are to be + used as SCL / SDA. Any of the previous I2C_xxx macros will + have GPIO-based defaults assigned to them as appropriate. + + You should define these to the GPIO value as given directly to + the generic GPIO functions. + CONFIG_SYS_I2C_INIT_BOARD When a board is reset during an i2c bus transfer @@ -1509,6 +1556,17 @@ The following options need to be configured: custom i2c_init_board() routine in boards/xxx/board.c is run early in the boot sequence. + CONFIG_SYS_I2C_BOARD_LATE_INIT + + An alternative to CONFIG_SYS_I2C_INIT_BOARD. If this option is + defined a custom i2c_board_late_init() routine in + boards/xxx/board.c is run AFTER the operations in i2c_init() + is completed. This callpoint can be used to unreset i2c bus + using CPU i2c controller register accesses for CPUs whose i2c + controller provide such a method. It is called at the end of + i2c_init() to allow i2c_init operations to setup the i2c bus + controller on the CPU (e.g. setting bus speed & slave address). + CONFIG_I2CFAST (PPC405GP|PPC405EP only) This option enables configuration of bi_iic_fast[] flags @@ -1629,6 +1687,11 @@ The following options need to be configured: SPI EEPROM, also an instance works with Crystal A/D and D/As on the SACSng board) + CONFIG_SH_SPI + + Enables the driver for SPI controller on SuperH. Currently + only SH7757 is supported. + CONFIG_SPI_X Enables extended (16-bit) SPI EEPROM addressing. @@ -1778,7 +1841,7 @@ The following options need to be configured: ETX094, IVMS8, IVML24, SPD8xx, TQM8xxL, HERMES, IP860, RPXlite, LWMON, LANTEC, - PCU_E, FLAGADM, TQM8260 + FLAGADM, TQM8260 - Error Recovery: CONFIG_PANIC_HANG @@ -1966,7 +2029,7 @@ Legacy uImage format: 15 arch//lib/bootm.c All preparation done, transferring control to OS - -30 arch/ppc/lib/board.c Fatal error, hang the system + -30 arch/powerpc/lib/board.c Fatal error, hang the system -31 post/post.c POST test failed, detected by post_output_backlog() -32 post/post.c POST test failed, detected by post_run_single() @@ -2245,7 +2308,7 @@ Configuration Settings: - CONFIG_SYS_MONITOR_BASE: Physical start address of boot monitor code (set by make config files to be same as the text base address - (TEXT_BASE) used when linking) - same as + (CONFIG_SYS_TEXT_BASE) used when linking) - same as CONFIG_SYS_FLASH_BASE when booting from flash. - CONFIG_SYS_MONITOR_LEN: @@ -2272,6 +2335,19 @@ Configuration Settings: all data for the Linux kernel must be between "bootm_low" and "bootm_low" + CONFIG_SYS_BOOTMAPSZ. +- CONFIG_SYS_BOOT_RAMDISK_HIGH: + Enable initrd_high functionality. If defined then the + initrd_high feature is enabled and the bootm ramdisk subcommand + is enabled. + +- CONFIG_SYS_BOOT_GET_CMDLINE: + Enables allocating and saving kernel cmdline in space between + "bootm_low" and "bootm_low" + BOOTMAPSZ. + +- CONFIG_SYS_BOOT_GET_KBD: + Enables allocating and saving a kernel copy of the bd_info in + space between "bootm_low" and "bootm_low" + BOOTMAPSZ. + - CONFIG_SYS_MAX_FLASH_BANKS: Max number of Flash memory banks @@ -2346,6 +2422,14 @@ Configuration Settings: on high Ethernet traffic. Defaults to 4 if not defined. +- CONFIG_ENV_MAX_ENTRIES + + Maximum number of entries in the hash table that is used + internally to store the environment settings. The default + setting is supposed to be generous and should work in most + cases. This setting can be used to tune behaviour; see + lib/hashtable.c for details. + The following definitions that deal with the placement and management of environment data (variable area); in general, we support the following configurations: @@ -2496,7 +2580,7 @@ to save the current settings. I2C muxes, you can define here, how to reach this EEPROM. For example: - #define CONFIG_I2C_ENV_EEPROM_BUS "pca9547:70:d\0" + #define CONFIG_I2C_ENV_EEPROM_BUS "pca9547:70:d\0" EEPROM which holds the environment, is reached over a pca9547 i2c mux with address 0x70, channel 3. @@ -2523,18 +2607,32 @@ to save the current settings. - CONFIG_ENV_SIZE: These two #defines specify the offset and size of the environment - area within the first NAND device. + area within the first NAND device. CONFIG_ENV_OFFSET must be + aligned to an erase block boundary. - - CONFIG_ENV_OFFSET_REDUND + - CONFIG_ENV_OFFSET_REDUND (optional): This setting describes a second storage area of CONFIG_ENV_SIZE - size used to hold a redundant copy of the environment data, - so that there is a valid backup copy in case there is a - power failure during a "saveenv" operation. + size used to hold a redundant copy of the environment data, so + that there is a valid backup copy in case there is a power failure + during a "saveenv" operation. CONFIG_ENV_OFFSET_RENDUND must be + aligned to an erase block boundary. + + - CONFIG_ENV_RANGE (optional): + + Specifies the length of the region in which the environment + can be written. This should be a multiple of the NAND device's + block size. Specifying a range with more erase blocks than + are needed to hold CONFIG_ENV_SIZE allows bad blocks within + the range to be avoided. - Note: CONFIG_ENV_OFFSET and CONFIG_ENV_OFFSET_REDUND must be aligned - to a block boundary, and CONFIG_ENV_SIZE must be a multiple of - the NAND devices block size. + - CONFIG_ENV_OFFSET_OOB (optional): + + Enables support for dynamically retrieving the offset of the + environment from block zero's out-of-band data. The + "nand env.oob" command can be used to record this offset. + Currently, CONFIG_ENV_OFFSET_REDUND is not supported when + using CONFIG_ENV_OFFSET_OOB. - CONFIG_NAND_ENV_DST @@ -2554,7 +2652,7 @@ to save the current settings. Please note that the environment is read-only until the monitor has been relocated to RAM and a RAM copy of the environment has been -created; also, when using EEPROM you will have to use getenv_r() +created; also, when using EEPROM you will have to use getenv_f() until then to read environment variables. The environment is protected by a CRC32 checksum. Before the monitor @@ -2648,7 +2746,7 @@ Low Level (hardware related) configuration options: area defined by CONFIG_SYS_INIT_RAM_ADDR. Usually CONFIG_SYS_GBL_DATA_OFFSET is chosen such that the initial data is located at the end of the available space - (sometimes written as (CONFIG_SYS_INIT_RAM_END - + (sometimes written as (CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_INIT_DATA_SIZE), and the initial stack is just below that area (growing from (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) downward. @@ -2727,12 +2825,30 @@ Low Level (hardware related) configuration options: CONFIG_SYS_PCI_MSTR_MEMIO_SIZE, CONFIG_SYS_POCMR1_MASK_ATTRIB, CONFIG_SYS_PCI_MSTR_IO_LOCAL, CONFIG_SYS_PCI_MSTR_IO_BUS, CONFIG_SYS_CPU_PCI_IO_START, CONFIG_SYS_PCI_MSTR_IO_SIZE, CONFIG_SYS_POCMR2_MASK_ATTRIB: (MPC826x only) - Overrides the default PCI memory map in arch/ppc/cpu/mpc8260/pci.c if set. + Overrides the default PCI memory map in arch/powerpc/cpu/mpc8260/pci.c if set. - CONFIG_PCI_DISABLE_PCIE: Disable PCI-Express on systems where it is supported but not required. +- CONFIG_SYS_SRIO: + Chip has SRIO or not + +- CONFIG_SRIO1: + Board has SRIO 1 port available + +- CONFIG_SRIO2: + Board has SRIO 2 port available + +- CONFIG_SYS_SRIOn_MEM_VIRT: + Virtual Address of SRIO port 'n' memory region + +- CONFIG_SYS_SRIOn_MEM_PHYS: + Physical Address of SRIO port 'n' memory region + +- CONFIG_SYS_SRIOn_MEM_SIZE: + Size of SRIO port 'n' memory region + - CONFIG_SPD_EEPROM Get DDR timing information from an I2C EEPROM. Common with pluggable memory modules such as SODIMMs @@ -2798,19 +2914,17 @@ Low Level (hardware related) configuration options: globally (CONFIG_CMD_MEM). - CONFIG_SKIP_LOWLEVEL_INIT -- CONFIG_SKIP_RELOCATE_UBOOT + [ARM only] If this variable is defined, then certain + low level initializations (like setting up the memory + controller) are omitted and/or U-Boot does not + relocate itself into RAM. - [ARM only] If these variables are defined, then - certain low level initializations (like setting up - the memory controller) are omitted and/or U-Boot does - not relocate itself into RAM. - Normally these variables MUST NOT be defined. The - only exception is when U-Boot is loaded (to RAM) by - some other boot loader or by a debugger which - performs these initializations itself. + Normally this variable MUST NOT be defined. The only + exception is when U-Boot is loaded (to RAM) by some + other boot loader or by a debugger which performs + these initializations itself. - CONFIG_PRELOADER - Modifies the behaviour of start.S when compiling a loader that is executed before the actual U-Boot. E.g. when compiling a NAND SPL. @@ -3140,10 +3254,10 @@ List of environment variables (most likely not complete): interface is currently active. For example you can do the following - => setenv ethact FEC ETHERNET - => ping 192.168.0.1 # traffic sent on FEC ETHERNET - => setenv ethact SCC ETHERNET - => ping 10.0.0.1 # traffic sent on SCC ETHERNET + => setenv ethact FEC + => ping 192.168.0.1 # traffic sent on FEC + => setenv ethact SCC + => ping 10.0.0.1 # traffic sent on SCC ethrotate - When set to "no" U-Boot does not go through all available network interfaces. @@ -3292,6 +3406,11 @@ o If both the SROM and the environment contain a MAC address, and the o If neither SROM nor the environment contain a MAC address, an error is raised. +If Ethernet drivers implement the 'write_hwaddr' function, valid MAC addresses +will be programmed into hardware as part of the initialization process. This +may be skipped by setting the appropriate 'ethmacskip' environment variable. +The naming convention is as follows: +"ethmacskip" (=>eth0), "eth1macskip" (=>eth1) etc. Image Formats: ============== @@ -3321,8 +3440,8 @@ details; basically, the header defines the following image properties: Currently supported: Linux, NetBSD, VxWorks, QNX, RTEMS, LynxOS, INTEGRITY). * Target CPU Architecture (Provisions for Alpha, ARM, AVR32, Intel x86, - IA64, MIPS, NIOS, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit; - Currently supported: ARM, AVR32, Intel x86, MIPS, NIOS, PowerPC). + IA64, MIPS, Nios II, PowerPC, IBM S390, SuperH, Sparc, Sparc 64 Bit; + Currently supported: ARM, AVR32, Intel x86, MIPS, Nios II, PowerPC). * Compression Type (uncompressed, gzip, bzip2) * Load Address * Entry Point @@ -3373,7 +3492,7 @@ configure the Linux device drivers for use with your target hardware (no, we don't intend to provide a full virtual machine interface to Linux :-). -But now you can ignore ALL boot loader code (in arch/ppc/mbxboot). +But now you can ignore ALL boot loader code (in arch/powerpc/mbxboot). Just make sure your machine specific header file (for instance include/asm-ppc/tqm8xx.h) includes the same definition of the Board @@ -3471,7 +3590,7 @@ So a typical call to build a U-Boot image would read: -> tools/mkimage -n '2.4.4 kernel for TQM850L' \ > -A ppc -O linux -T kernel -C gzip -a 0 -e 0 \ - > -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux.gz \ + > -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux.gz \ > examples/uImage.TQM850L Image Name: 2.4.4 kernel for TQM850L Created: Wed Jul 19 02:34:59 2000 @@ -3495,10 +3614,10 @@ speed for memory and install an UNCOMPRESSED image instead: this needs more space in Flash, but boots much faster since it does not need to be uncompressed: - -> gunzip /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux.gz + -> gunzip /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux.gz -> tools/mkimage -n '2.4.4 kernel for TQM850L' \ > -A ppc -O linux -T kernel -C none -a 0 -e 0 \ - > -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/ppc/coffboot/vmlinux \ + > -d /opt/elsk/ppc_8xx/usr/src/linux-2.4.4/arch/powerpc/coffboot/vmlinux \ > examples/uImage.TQM850L-uncompressed Image Name: 2.4.4 kernel for TQM850L Created: Wed Jul 19 02:34:59 2000 @@ -4007,6 +4126,14 @@ On ARM, the following registers are used: ==> U-Boot will use R8 to hold a pointer to the global data +On Nios II, the ABI is documented here: + http://www.altera.com/literature/hb/nios2/n2cpu_nii51016.pdf + + ==> U-Boot will use gp to hold a pointer to the global data + + Note: on Nios II, we give "-G0" option to gcc and don't use gp + to access small data sections, so gp is free. + NOTE: DECLARE_GLOBAL_DATA_PTR must be used with file-global scope, or current versions of GCC may "optimize" the code too much.