X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=README;h=43f307f30fd8ce3b1fd5a0ee098399e7ff2bb2f4;hb=ccf5648e0e3c4a61fe57109b39bf64c1cc1418c9;hp=95f2d9d2fe97026f2200dfee9f61c500b6aaa3f9;hpb=0741701acf00749672f75f4c196dabd8b235f741;p=oweals%2Fu-boot.git diff --git a/README b/README index 95f2d9d2fe..43f307f30f 100644 --- a/README +++ b/README @@ -611,6 +611,9 @@ The following options need to be configured: CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS Number of controllers used for other than main memory. + CONFIG_SYS_FSL_HAS_DP_DDR + Defines the SoC has DP-DDR used for DPAA. + CONFIG_SYS_FSL_SEC_BE Defines the SEC controller register space as Big Endian @@ -681,8 +684,10 @@ The following options need to be configured: CONFIG_ARM_ERRATA_742230 CONFIG_ARM_ERRATA_743622 CONFIG_ARM_ERRATA_751472 - CONFIG_ARM_ERRATA_794072 CONFIG_ARM_ERRATA_761320 + CONFIG_ARM_ERRATA_773022 + CONFIG_ARM_ERRATA_774769 + CONFIG_ARM_ERRATA_794072 If set, the workarounds for these ARM errata are applied early during U-Boot startup. Note that these options force the @@ -794,18 +799,10 @@ The following options need to be configured: - vxWorks boot parameters: bootvx constructs a valid bootline using the following - environments variables: bootfile, ipaddr, serverip, hostname. + environments variables: bootdev, bootfile, ipaddr, netmask, + serverip, gatewayip, hostname, othbootargs. It loads the vxWorks image pointed bootfile. - CONFIG_SYS_VXWORKS_BOOT_DEVICE - The vxworks device name - CONFIG_SYS_VXWORKS_MAC_PTR - Ethernet 6 byte MA -address - CONFIG_SYS_VXWORKS_SERVERNAME - Name of the server - CONFIG_SYS_VXWORKS_BOOT_ADDR - Address of boot parameters - - CONFIG_SYS_VXWORKS_ADD_PARAMS - - Add it at the end of the bootline. E.g "u=username pw=secret" - Note: If a "bootargs" environment is defined, it will overwride the defaults discussed just above. @@ -840,18 +837,6 @@ The following options need to be configured: define this to a list of base addresses for each (supported) port. See e.g. include/configs/versatile.h - CONFIG_PL011_SERIAL_RLCR - - Some vendor versions of PL011 serial ports (e.g. ST-Ericsson U8500) - have separate receive and transmit line control registers. Set - this variable to initialize the extra register. - - CONFIG_PL011_SERIAL_FLUSH_ON_INIT - - On some platforms (e.g. U8500) U-Boot is loaded by a second stage - boot loader that has already initialized the UART. Define this - variable to flush the UART at init time. - CONFIG_SERIAL_HW_FLOW_CONTROL Define this variable to enable hw flow control in serial driver. @@ -885,18 +870,11 @@ The following options need to be configured: (0-5, cf. cfb_console.c) VIDEO_FB_ADRS framebuffer address VIDEO_KBD_INIT_FCT keyboard int fct - (i.e. i8042_kbd_init()) + (i.e. rx51_kp_init()) VIDEO_TSTC_FCT test char fct - (i.e. i8042_tstc) + (i.e. rx51_kp_tstc) VIDEO_GETC_FCT get char fct - (i.e. i8042_getc) - CONFIG_CONSOLE_CURSOR cursor drawing on/off - (requires blink timer - cf. i8042.c) - CONFIG_SYS_CONSOLE_BLINK_COUNT blink interval (cf. i8042.c) - CONFIG_CONSOLE_TIME display time/date info in - upper right corner - (requires CONFIG_CMD_DATE) + (i.e. rx51_kp_getc) CONFIG_VIDEO_LOGO display Linux logo in upper left corner CONFIG_VIDEO_BMP_LOGO use bmp_logo.h instead of @@ -1382,9 +1360,6 @@ The following options need to be configured: Management command for E1000 devices. When used on devices with SPI support you can reprogram the EEPROM from U-Boot. - CONFIG_E1000_FALLBACK_MAC - default MAC for empty EEPROM after production. - CONFIG_EEPRO100 Support for Intel 82557/82559/82559ER chips. Optional CONFIG_EEPRO100_SROM_WRITE enables EEPROM @@ -1493,16 +1468,10 @@ The following options need to be configured: CONFIG_TPM Support TPM devices. - CONFIG_TPM_TIS_I2C - Support for i2c bus TPM devices. Only one device + CONFIG_TPM_TIS_INFINEON + Support for Infineon i2c bus TPM devices. Only one device per system is supported at this time. - CONFIG_TPM_TIS_I2C_BUS_NUMBER - Define the the i2c bus number for the TPM device - - CONFIG_TPM_TIS_I2C_SLAVE_ADDRESS - Define the TPM's address on the i2c bus - CONFIG_TPM_TIS_I2C_BURST_LIMITATION Define the burst count bytes upper limit @@ -1801,21 +1770,15 @@ CBFS (Coreboot Filesystem) support a default value of 65536 will be defined. - Keyboard Support: - CONFIG_ISA_KEYBOARD + See Kconfig help for available keyboard drivers. - Define this to enable standard (PC-Style) keyboard - support - - CONFIG_I8042_KBD - Standard PC keyboard driver with US (is default) and - GERMAN key layout (switch via environment 'keymap=de') support. - Export function i8042_kbd_init, i8042_tstc and i8042_getc - for cfb_console. Supports cursor blinking. + CONFIG_KEYBOARD - CONFIG_CROS_EC_KEYB - Enables a Chrome OS keyboard using the CROS_EC interface. - This uses CROS_EC to communicate with a second microcontroller - which provides key scans on request. + Define this to enable a custom keyboard support. + This simply calls drv_keyboard_init() which must be + defined in your board-specific files. This option is deprecated + and is only used by novena. For new boards, use driver model + instead. - Video support: CONFIG_VIDEO @@ -1876,15 +1839,6 @@ CBFS (Coreboot Filesystem) support boot. See the documentation file README.video for a description of this variable. - -- Keyboard Support: - CONFIG_KEYBOARD - - Define this to enable a custom keyboard support. - This simply calls drv_keyboard_init() which must be - defined in your board-specific files. - The only board using this so far is RBC823. - - LCD Support: CONFIG_LCD Define this to enable LCD support (for output to LCD @@ -2380,16 +2334,20 @@ CBFS (Coreboot Filesystem) support - drivers/i2c/i2c_mxc.c - activate this driver with CONFIG_SYS_I2C_MXC + - enable bus 1 with CONFIG_SYS_I2C_MXC_I2C1 + - enable bus 2 with CONFIG_SYS_I2C_MXC_I2C2 + - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3 + - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4 - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE + - define speed for bus 4 with CONFIG_SYS_MXC_I2C4_SPEED + - define slave for bus 4 with CONFIG_SYS_MXC_I2C4_SLAVE If those defines are not set, default value is 100000 for speed, and 0 for slave. - - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3 - - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4 - drivers/i2c/rcar_i2c.c: - activate this driver with CONFIG_SYS_I2C_RCAR @@ -2461,6 +2419,15 @@ CBFS (Coreboot Filesystem) support - CONFIG_SYS_I2C_IHS_CH3 activate hardware channel 3 - CONFIG_SYS_I2C_IHS_SPEED_3 speed channel 3 - CONFIG_SYS_I2C_IHS_SLAVE_3 slave addr channel 3 + - activate dual channel with CONFIG_SYS_I2C_IHS_DUAL + - CONFIG_SYS_I2C_IHS_SPEED_0_1 speed channel 0_1 + - CONFIG_SYS_I2C_IHS_SLAVE_0_1 slave addr channel 0_1 + - CONFIG_SYS_I2C_IHS_SPEED_1_1 speed channel 1_1 + - CONFIG_SYS_I2C_IHS_SLAVE_1_1 slave addr channel 1_1 + - CONFIG_SYS_I2C_IHS_SPEED_2_1 speed channel 2_1 + - CONFIG_SYS_I2C_IHS_SLAVE_2_1 slave addr channel 2_1 + - CONFIG_SYS_I2C_IHS_SPEED_3_1 speed channel 3_1 + - CONFIG_SYS_I2C_IHS_SLAVE_3_1 slave addr channel 3_1 additional defines: @@ -2728,11 +2695,6 @@ CBFS (Coreboot Filesystem) support Enables the driver for SPI controller on SuperH. Currently only SH7757 is supported. - CONFIG_SPI_X - - Enables extended (16-bit) SPI EEPROM addressing. - (symmetrical to CONFIG_I2C_X) - CONFIG_SOFT_SPI Enables a software (bit-bang) SPI driver rather than @@ -3517,6 +3479,10 @@ FIT uImage format: without a fastmap. default: 0 + CONFIG_MTD_UBI_FM_DEBUG + Enable UBI fastmap debug + default: 0 + - UBIFS support CONFIG_CMD_UBIFS @@ -3587,6 +3553,9 @@ FIT uImage format: CONFIG_SYS_SPL_MALLOC_START Starting address of the malloc pool used in SPL. + When this option is set the full malloc is used in SPL and + it is set up by spl_init() and before that, the simple malloc() + can be used if CONFIG_SYS_MALLOC_F is defined. CONFIG_SYS_SPL_MALLOC_SIZE The size of the malloc pool used in SPL. @@ -3900,7 +3869,15 @@ Configuration Settings: Scratch address used by the alternate memory test You only need to set this if address zero isn't writeable -- CONFIG_SYS_MEM_TOP_HIDE (PPC only): +- CONFIG_SYS_MEM_RESERVE_SECURE + If defined, the size of CONFIG_SYS_MEM_RESERVE_SECURE memory + is substracted from total RAM and won't be reported to OS. + This memory can be used as secure memory. A variable + gd->secure_ram is used to track the location. In systems + the RAM base is not zero, or RAM is divided into banks, + this variable needs to be recalcuated to get the address. + +- CONFIG_SYS_MEM_TOP_HIDE: If CONFIG_SYS_MEM_TOP_HIDE is defined in the board config header, this specified memory area will get subtracted from the top (end) of RAM and won't get "touched" at all by U-Boot. By @@ -5079,8 +5056,8 @@ This firmware often needs to be loaded during U-Boot booting. - CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE Define minimum DDR size required for debug server image -- CONFIG_SYS_MEM_TOP_HIDE_MIN - Define minimum DDR size to be hided from top of the DDR memory +- CONFIG_SYS_MC_RSV_MEM_ALIGN + Define alignment of reserved memory MC requires Reproducible builds ------------------- @@ -5473,10 +5450,10 @@ List of environment variables (most likely not complete): unset, then it will be made silent if the U-Boot console is silent. - tftpsrcport - If this is set, the value is used for TFTP's + tftpsrcp - If this is set, the value is used for TFTP's UDP source port. - tftpdstport - If this is set, the value is used for TFTP's UDP + tftpdstp - If this is set, the value is used for TFTP's UDP destination port instead of the Well Know Port 69. tftpblocksize - Block size to use for TFTP transfers; if not set, @@ -5490,6 +5467,14 @@ List of environment variables (most likely not complete): faster in networks with high packet loss rates or with unreliable TFTP servers. + tftptimeoutcountmax - maximum count of TFTP timeouts (no + unit, minimum value = 0). Defines how many timeouts + can happen during a single file transfer before that + transfer is aborted. The default is 10, and 0 means + 'no timeouts allowed'. Increasing this value may help + downloads succeed with high packet loss rates, or with + unreliable TFTP servers or client hardware. + vlan - When set to a value < 4095 the traffic over Ethernet is encapsulated/received over 802.1q VLAN tagged frames.