X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;f=README;h=0dc657d0a583739a817f07f52e0f9572b30c8861;hb=3b82402597622d04d0b0eb7b382068fe8456c7f5;hp=4e0ff9f74e5991843acc2983904d675bb79f735d;hpb=26473945ad6667183296e7edee2a65edf31bb6f7;p=oweals%2Fu-boot.git diff --git a/README b/README index 4e0ff9f74e..0dc657d0a5 100644 --- a/README +++ b/README @@ -681,8 +681,10 @@ The following options need to be configured: CONFIG_ARM_ERRATA_742230 CONFIG_ARM_ERRATA_743622 CONFIG_ARM_ERRATA_751472 - CONFIG_ARM_ERRATA_794072 CONFIG_ARM_ERRATA_761320 + CONFIG_ARM_ERRATA_773022 + CONFIG_ARM_ERRATA_774769 + CONFIG_ARM_ERRATA_794072 If set, the workarounds for these ARM errata are applied early during U-Boot startup. Note that these options force the @@ -705,6 +707,7 @@ The following options need to be configured: CONFIG_ARM_ERRATA_454179 CONFIG_ARM_ERRATA_621766 CONFIG_ARM_ERRATA_798870 + CONFIG_ARM_ERRATA_801819 - Tegra SoC options: CONFIG_TEGRA_SUPPORT_NON_SECURE @@ -839,18 +842,6 @@ The following options need to be configured: define this to a list of base addresses for each (supported) port. See e.g. include/configs/versatile.h - CONFIG_PL011_SERIAL_RLCR - - Some vendor versions of PL011 serial ports (e.g. ST-Ericsson U8500) - have separate receive and transmit line control registers. Set - this variable to initialize the extra register. - - CONFIG_PL011_SERIAL_FLUSH_ON_INIT - - On some platforms (e.g. U8500) U-Boot is loaded by a second stage - boot loader that has already initialized the UART. Define this - variable to flush the UART at init time. - CONFIG_SERIAL_HW_FLOW_CONTROL Define this variable to enable hw flow control in serial driver. @@ -1381,9 +1372,6 @@ The following options need to be configured: Management command for E1000 devices. When used on devices with SPI support you can reprogram the EEPROM from U-Boot. - CONFIG_E1000_FALLBACK_MAC - default MAC for empty EEPROM after production. - CONFIG_EEPRO100 Support for Intel 82557/82559/82559ER chips. Optional CONFIG_EEPRO100_SROM_WRITE enables EEPROM @@ -1496,12 +1484,6 @@ The following options need to be configured: Support for i2c bus TPM devices. Only one device per system is supported at this time. - CONFIG_TPM_TIS_I2C_BUS_NUMBER - Define the the i2c bus number for the TPM device - - CONFIG_TPM_TIS_I2C_SLAVE_ADDRESS - Define the TPM's address on the i2c bus - CONFIG_TPM_TIS_I2C_BURST_LIMITATION Define the burst count bytes upper limit @@ -2379,16 +2361,20 @@ CBFS (Coreboot Filesystem) support - drivers/i2c/i2c_mxc.c - activate this driver with CONFIG_SYS_I2C_MXC + - enable bus 1 with CONFIG_SYS_I2C_MXC_I2C1 + - enable bus 2 with CONFIG_SYS_I2C_MXC_I2C2 + - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3 + - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4 - define speed for bus 1 with CONFIG_SYS_MXC_I2C1_SPEED - define slave for bus 1 with CONFIG_SYS_MXC_I2C1_SLAVE - define speed for bus 2 with CONFIG_SYS_MXC_I2C2_SPEED - define slave for bus 2 with CONFIG_SYS_MXC_I2C2_SLAVE - define speed for bus 3 with CONFIG_SYS_MXC_I2C3_SPEED - define slave for bus 3 with CONFIG_SYS_MXC_I2C3_SLAVE + - define speed for bus 4 with CONFIG_SYS_MXC_I2C4_SPEED + - define slave for bus 4 with CONFIG_SYS_MXC_I2C4_SLAVE If those defines are not set, default value is 100000 for speed, and 0 for slave. - - enable bus 3 with CONFIG_SYS_I2C_MXC_I2C3 - - enable bus 4 with CONFIG_SYS_I2C_MXC_I2C4 - drivers/i2c/rcar_i2c.c: - activate this driver with CONFIG_SYS_I2C_RCAR @@ -5081,6 +5067,18 @@ This firmware often needs to be loaded during U-Boot booting. - CONFIG_SYS_MEM_TOP_HIDE_MIN Define minimum DDR size to be hided from top of the DDR memory +Reproducible builds +------------------- + +In order to achieve reproducible builds, timestamps used in the U-Boot build +process have to be set to a fixed value. + +This is done using the SOURCE_DATE_EPOCH environment variable. +SOURCE_DATE_EPOCH is to be set on the build host's shell, not as a configuration +option for U-Boot or an environment variable in U-Boot. + +SOURCE_DATE_EPOCH should be set to a number of seconds since the epoch, in UTC. + Building the Software: ======================