X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;ds=sidebyside;f=include%2Fconfigs%2Ftegra186-common.h;h=b4936cc731f77fd45d13e549887e6b65aad4f55e;hb=943be15974013a7fdd833cd4efd75705976a9f33;hp=aa7b9d038a7e3be5bb1531f80477959e9a4fae5a;hpb=cc749523ae1adec3856f2b7fe77a6d856da4652a;p=oweals%2Fu-boot.git

diff --git a/include/configs/tegra186-common.h b/include/configs/tegra186-common.h
index aa7b9d038a..b4936cc731 100644
--- a/include/configs/tegra186-common.h
+++ b/include/configs/tegra186-common.h
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright 2013-2016, NVIDIA CORPORATION.
- *
- * SPDX-License-Identifier: GPL-2.0
  */
 
 #ifndef _TEGRA186_COMMON_H_
@@ -9,25 +8,15 @@
 
 #include "tegra-common.h"
 
-/* Cortex-A57 uses a cache line size of 64 bytes */
-#define CONFIG_SYS_CACHELINE_SIZE	64
-
 /*
  * NS16550 Configuration
  */
 #define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */
 
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_STACKBASE	0x82800000	/* 40MB */
-
 /*-----------------------------------------------------------------------
  * Physical Memory Map
  */
 
-#define CONFIG_SYS_TEXT_BASE	0x80080000
-
 /* Generic Interrupt Controller */
 #define CONFIG_GICV2
 
@@ -63,9 +52,4 @@
 	"fdt_addr_r=0x82000000\0" \
 	"ramdisk_addr_r=0x82100000\0"
 
-/* Defines for SPL */
-#define CONFIG_SPL_TEXT_BASE		0x80108000
-#define CONFIG_SYS_SPL_MALLOC_START	0x80090000
-#define CONFIG_SPL_STACK		0x800ffffc
-
 #endif