X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;ds=sidebyside;f=include%2Fconfigs%2Fstrider.h;h=ac9fce80cec3127b55b3806cf12fe2bbdaf7c6c7;hb=69acc36864d55229b9520bb620fdc546488ab78d;hp=184396e0379ced3af93e4916b20d418d6bf4ce13;hpb=5d2f4c9641bae821d421a3d362596f84905daca2;p=oweals%2Fu-boot.git

diff --git a/include/configs/strider.h b/include/configs/strider.h
index 184396e037..ac9fce80ce 100644
--- a/include/configs/strider.h
+++ b/include/configs/strider.h
@@ -12,59 +12,19 @@
  * High Level Configuration Options
  */
 #define CONFIG_E300		1 /* E300 family */
-#define CONFIG_MPC83xx		1 /* MPC83xx family */
 
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
 
-/*
- * System IO Config
- */
-#define CONFIG_SYS_SICRH (\
-	SICRH_ESDHC_A_SD |\
-	SICRH_ESDHC_B_SD |\
-	SICRH_ESDHC_C_SD |\
-	SICRH_GPIO_A_GPIO |\
-	SICRH_GPIO_B_GPIO |\
-	SICRH_IEEE1588_A_GPIO |\
-	SICRH_USB |\
-	SICRH_GTM_GPIO |\
-	SICRH_IEEE1588_B_GPIO |\
-	SICRH_ETSEC2_GPIO |\
-	SICRH_GPIOSEL_1 |\
-	SICRH_TMROBI_V3P3 |\
-	SICRH_TSOBI1_V2P5 |\
-	SICRH_TSOBI2_V2P5)	/* 0x0037f103 */
-#define CONFIG_SYS_SICRL (\
-	SICRL_SPI_PF0 |\
-	SICRL_UART_PF0 |\
-	SICRL_IRQ_PF0 |\
-	SICRL_I2C2_PF0 |\
-	SICRL_ETSEC1_TX_CLK)	/* 0x00000000 */
-
-/*
- * IMMR new address
- */
-#define CONFIG_SYS_IMMR		0xE0000000
-
 /*
  * SERDES
  */
 #define CONFIG_FSL_SERDES
 #define CONFIG_FSL_SERDES1	0xe3000
 
-/*
- * Arbiter Setup
- */
-#define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
-#define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
-#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */
-
 /*
  * DDR Setup
  */
-#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
-#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
+#define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
 #define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
 				| DDRCDR_PZ_LOZ \
@@ -150,13 +110,6 @@
 #define CONFIG_SYS_GBL_DATA_OFFSET	\
 	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
-/*
- * Local Bus Configuration & Clock Setup
- */
-#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
-#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
-#define CONFIG_SYS_LBC_LBCR		0x00040000
-
 /*
  * FLASH on the Local Bus
  */
@@ -167,19 +120,6 @@
 #define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
 #define CONFIG_SYS_FLASH_SIZE		8 /* FLASH size is up to 8M */
 
-/* Window base at flash base */
-#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
-				| BR_PS_16	/* 16 bit port */ \
-				| BR_MS_GPCM	/* MSEL = GPCM */ \
-				| BR_V)		/* valid */
-#define CONFIG_SYS_OR0_PRELIM	(OR_AM_8MB \
-				| OR_UPM_XAM \
-				| OR_GPCM_CSNT \
-				| OR_GPCM_ACS_DIV2 \
-				| OR_GPCM_XACS \
-				| OR_GPCM_SCY_15 \
-				| OR_GPCM_TRLX_SET \
-				| OR_GPCM_EHTR_SET)
 
 #define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
 #define CONFIG_SYS_MAX_FLASH_SECT	135
@@ -187,26 +127,6 @@
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
 
-/*
- * FPGA
- */
-#define CONFIG_SYS_FPGA0_BASE		0xE0600000
-#define CONFIG_SYS_FPGA0_SIZE		1 /* FPGA size is 1M */
-
-/* Window base at FPGA base */
-#define CONFIG_SYS_BR1_PRELIM	(CONFIG_SYS_FPGA0_BASE \
-				| BR_PS_16	/* 16 bit port */ \
-				| BR_MS_GPCM	/* MSEL = GPCM */ \
-				| BR_V)		/* valid */
-
-#define CONFIG_SYS_OR1_PRELIM   (OR_AM_1MB \
-				| OR_UPM_XAM \
-				| OR_GPCM_CSNT \
-				| OR_GPCM_SCY_5 \
-				| OR_GPCM_TRLX_CLEAR \
-				| OR_GPCM_EHTR_CLEAR)
-
-#define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
 #define CONFIG_SYS_FPGA_DONE(k)		0x0010
 
 #define CONFIG_SYS_FPGA_COUNT		1
@@ -464,16 +384,6 @@ void fpga_control_clear(unsigned int bus, int pin);
 /*
  * Environment
  */
-#if 1
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
-				 CONFIG_SYS_MONITOR_LEN)
-#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE
-#else
-#define CONFIG_ENV_SIZE		0x2000		/* 8KB */
-#endif
 
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
@@ -499,15 +409,6 @@ void fpga_control_clear(unsigned int bus, int pin);
  */
 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
 
-/*
- * Core HID Setup
- */
-#define CONFIG_SYS_HID0_INIT	0x000000000
-#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
-				 HID0_ENABLE_INSTRUCTION_CACHE | \
-				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
-#define CONFIG_SYS_HID2		HID2_HBE
-
 /*
  * Environment Configuration
  */
@@ -525,8 +426,6 @@ void fpga_control_clear(unsigned int bus, int pin);
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
 #define CONFIG_BOOTFILE		"uImage"
 
-#define CONFIG_PREBOOT		/* enable preboot variable */
-
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
 	"netdev=eth0\0"							\
 	"consoledev=ttyS1\0"						\