X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;ds=sidebyside;f=include%2Fconfigs%2Fads5121.h;h=d129ea317dc59b4cfa8375ba69657f73f6f28f02;hb=00b1883a4cac59d97cd297b1a3a398db85982865;hp=bb1efdf6deac7cb0991a4e7e344314463f4a7553;hpb=d4d1e9bee7c45ea8c513d3af697c864107f1c4d1;p=oweals%2Fu-boot.git

diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h
index bb1efdf6de..d129ea317d 100644
--- a/include/configs/ads5121.h
+++ b/include/configs/ads5121.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007 DENX Software Engineering
+ * (C) Copyright 2007, 2008 DENX Software Engineering
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -27,9 +27,7 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define DEBUG
-#undef DEBUG
-
+#define CONFIG_ADS5121 1
 /*
  * Memory map for the ADS5121 board:
  *
@@ -37,6 +35,9 @@
  * 0x3000_0000 - 0x3001_FFFF	SRAM (128 KB)
  * 0x8000_0000 - 0x803F_FFFF	IMMR (4 MB)
  * 0x8200_0000 - 0x8200_001F	CPLD (32 B)
+ * 0x8400_0000 - 0x82FF_FFFF	PCI I/O space (16 MB)
+ * 0xA000_0000 - 0xAFFF_FFFF	PCI memory space (256 MB)
+ * 0xB000_0000 - 0xBFFF_FFFF	PCI memory mapped I/O space (256 MB)
  * 0xFC00_0000 - 0xFFFF_FFFF	NOR Boot FLASH (64 MB)
  */
 
@@ -45,14 +46,30 @@
  */
 #define CONFIG_E300		1	/* E300 Family */
 #define CONFIG_MPC512X		1	/* MPC512X family */
+#define CONFIG_FSL_DIU_FB	1	/* FSL DIU */
+
+/* video */
+#undef CONFIG_VIDEO
 
-#undef CONFIG_PCI
+#if defined(CONFIG_VIDEO)
+#define CONFIG_CFB_CONSOLE
+#define CONFIG_VGA_AS_SINGLE_DEVICE
+#endif
 
+/* CONFIG_PCI is defined at config time */
+
+#ifdef CONFIG_ADS5121_REV2
 #define CFG_MPC512X_CLKIN	66000000	/* in Hz */
+#else
+#define CFG_MPC512X_CLKIN	33333333	/* in Hz */
+#define CONFIG_PCI
+#endif
 
 #define CONFIG_BOARD_EARLY_INIT_F		/* call board_early_init_f() */
+#define CONFIG_MISC_INIT_R
 
 #define CFG_IMMR		0x80000000
+#define CFG_DIU_ADDR		(CFG_IMMR+0x2100)
 
 #define CFG_MEMTEST_START	0x00200000      /* memtest region */
 #define CFG_MEMTEST_END		0x00400000
@@ -60,7 +77,11 @@
 /*
  * DDR Setup - manually set all parameters as there's no SPD etc.
  */
+#ifdef CONFIG_ADS5121_REV2
 #define CFG_DDR_SIZE		256		/* MB */
+#else
+#define CFG_DDR_SIZE		512		/* MB */
+#endif
 #define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
 #define CFG_SDRAM_BASE		CFG_DDR_BASE
 
@@ -108,63 +129,71 @@
  *	[09:05]	DRAM tRP:
  *	[04:00] DRAM tRPA
  */
-
-#define CFG_MDDRC_SYS_CFG	0xF8604200
-#define CFG_MDDRC_SYS_CFG_RUN	0xE8604200
-#define CFG_MDDRC_SYS_CFG_EN	0x30000000
-#define CFG_MDDRC_TIME_CFG0	0x0000281E
-#define CFG_MDDRC_TIME_CFG0_RUN	0x01F4281E
+#ifdef CONFIG_ADS5121_REV2
+#define CFG_MDDRC_SYS_CFG	0xF8604A00
+#define CFG_MDDRC_SYS_CFG_RUN	0xE8604A00
 #define CFG_MDDRC_TIME_CFG1	0x54EC1168
 #define CFG_MDDRC_TIME_CFG2	0x35210864
+#else
+#define CFG_MDDRC_SYS_CFG	 0xFA804A00
+#define CFG_MDDRC_SYS_CFG_RUN	 0xEA804A00
+#define CFG_MDDRC_TIME_CFG1	 0x68EC1168
+#define CFG_MDDRC_TIME_CFG2	 0x34310864
+#endif
+#define CFG_MDDRC_SYS_CFG_EN	0xF0000000
+#define CFG_MDDRC_TIME_CFG0	0x00003D2E
+#define CFG_MDDRC_TIME_CFG0_RUN	0x06183D2E
 
 #define CFG_MICRON_NOP		0x01380000
 #define CFG_MICRON_PCHG_ALL	0x01100400
-#define CFG_MICRON_MR		0x01000022
 #define CFG_MICRON_EM2		0x01020000
 #define CFG_MICRON_EM3		0x01030000
 #define CFG_MICRON_EN_DLL	0x01010000
-#define CFG_MICRON_RST_DLL	0x01000932
 #define CFG_MICRON_RFSH		0x01080000
-#define CFG_MICRON_INIT_DEV_OP	0x01000832
+#define CFG_MICRON_INIT_DEV_OP	0x01000432
 #define CFG_MICRON_OCD_DEFAULT	0x01010780
-#define CFG_MICRON_OCD_EXIT	0x01010400
 
 /* DDR Priority Manager Configuration */
-#define CFG_MDDRCGRP_PM_CFG1	0x000777AA
-#define CFG_MDDRCGRP_PM_CFG2	0x00000055
-#define CFG_MDDRCGRP_HIPRIO_CFG	0x00000000
-#define CFG_MDDRCGRP_LUT0_MU    0x11111117
-#define CFG_MDDRCGRP_LUT0_ML	0x7777777A
-#define CFG_MDDRCGRP_LUT1_MU    0x4444EEEE
-#define CFG_MDDRCGRP_LUT1_ML	0xEEEEEEEE
-#define CFG_MDDRCGRP_LUT2_MU    0x44444444
+#define CFG_MDDRCGRP_PM_CFG1	0x00077777
+#define CFG_MDDRCGRP_PM_CFG2	0x00000000
+#define CFG_MDDRCGRP_HIPRIO_CFG	0x00000001
+#define CFG_MDDRCGRP_LUT0_MU	0xFFEEDDCC
+#define CFG_MDDRCGRP_LUT0_ML	0xBBAAAAAA
+#define CFG_MDDRCGRP_LUT1_MU	0x66666666
+#define CFG_MDDRCGRP_LUT1_ML	0x55555555
+#define CFG_MDDRCGRP_LUT2_MU	0x44444444
 #define CFG_MDDRCGRP_LUT2_ML	0x44444444
-#define CFG_MDDRCGRP_LUT3_MU    0x55555555
+#define CFG_MDDRCGRP_LUT3_MU	0x55555555
 #define CFG_MDDRCGRP_LUT3_ML	0x55555558
-#define CFG_MDDRCGRP_LUT4_MU    0x11111111
-#define CFG_MDDRCGRP_LUT4_ML	0x1111117C
-#define CFG_MDDRCGRP_LUT0_AU    0x33333377
-#define CFG_MDDRCGRP_LUT0_AL	0x7777EEEE
-#define CFG_MDDRCGRP_LUT1_AU    0x11111111
-#define CFG_MDDRCGRP_LUT1_AL	0x11111111
-#define CFG_MDDRCGRP_LUT2_AU    0x11111111
+#define CFG_MDDRCGRP_LUT4_MU	0x11111111
+#define CFG_MDDRCGRP_LUT4_ML	0x11111122
+#define CFG_MDDRCGRP_LUT0_AU	0xaaaaaaaa
+#define CFG_MDDRCGRP_LUT0_AL	0xaaaaaaaa
+#define CFG_MDDRCGRP_LUT1_AU	0x66666666
+#define CFG_MDDRCGRP_LUT1_AL	0x66666666
+#define CFG_MDDRCGRP_LUT2_AU	0x11111111
 #define CFG_MDDRCGRP_LUT2_AL	0x11111111
-#define CFG_MDDRCGRP_LUT3_AU    0x11111111
+#define CFG_MDDRCGRP_LUT3_AU	0x11111111
 #define CFG_MDDRCGRP_LUT3_AL	0x11111111
-#define CFG_MDDRCGRP_LUT4_AU    0x11111111
+#define CFG_MDDRCGRP_LUT4_AU	0x11111111
 #define CFG_MDDRCGRP_LUT4_AL	0x11111111
 
 /*
  * NOR FLASH on the Local Bus
  */
+#undef CONFIG_BKUP_FLASH
 #define CFG_FLASH_CFI				/* use the Common Flash Interface */
-#define CFG_FLASH_CFI_DRIVER			/* use the CFI driver */
+#define CONFIG_FLASH_CFI_DRIVER			/* use the CFI driver */
+#ifdef CONFIG_BKUP_FLASH
+#define CFG_FLASH_BASE		0xFF800000	/* start of FLASH   */
+#define CFG_FLASH_SIZE		0x00800000	/* max flash size in bytes */
+#else
 #define CFG_FLASH_BASE		0xFC000000	/* start of FLASH   */
 #define CFG_FLASH_SIZE		0x04000000	/* max flash size in bytes */
+#endif
 #define CFG_FLASH_USE_BUFFER_WRITE
-
 #define CFG_MAX_FLASH_BANKS	1		/* number of banks */
-#define CFG_FLASH_BANKS_LIST 	{CFG_FLASH_BASE}
+#define CFG_FLASH_BANKS_LIST	{CFG_FLASH_BASE}
 #define CFG_MAX_FLASH_SECT	256		/* max sectors per device */
 
 #undef CFG_FLASH_CHECKSUM
@@ -192,7 +221,11 @@
 
 #define CFG_MONITOR_BASE	TEXT_BASE		/* Start of monitor */
 #define CFG_MONITOR_LEN		(256 * 1024)		/* Reserve 256 kB for Mon */
-#define CFG_MALLOC_LEN		(512 * 1024)		/* Reserved for malloc */
+#ifdef	CONFIG_FSL_DIU_FB
+#define CFG_MALLOC_LEN		(6 * 1024 * 1024)	/* Reserved for malloc */
+#else
+#define CFG_MALLOC_LEN		(512 * 1024)
+#endif
 
 /*
  * Serial Port
@@ -223,6 +256,31 @@
 #define CFG_PROMPT_HUSH_PS2 "> "
 #endif
 
+/*
+ * PCI
+ */
+#ifdef CONFIG_PCI
+
+/*
+ * General PCI
+ */
+#define CFG_PCI_MEM_BASE	0xA0000000
+#define CFG_PCI_MEM_PHYS	CFG_PCI_MEM_BASE
+#define CFG_PCI_MEM_SIZE	0x10000000	/* 256M */
+#define CFG_PCI_MMIO_BASE	(CFG_PCI_MEM_BASE + CFG_PCI_MEM_SIZE)
+#define CFG_PCI_MMIO_PHYS	CFG_PCI_MMIO_BASE
+#define CFG_PCI_MMIO_SIZE	0x10000000	/* 256M */
+#define CFG_PCI_IO_BASE		0x00000000
+#define CFG_PCI_IO_PHYS		0x84000000
+#define CFG_PCI_IO_SIZE		0x01000000	/* 16M */
+
+
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+
+#endif
+
 /* I2C */
 #define CONFIG_HARD_I2C			/* I2C with hardware support */
 #undef CONFIG_SOFT_I2C			/* so disable bit-banged I2C */
@@ -231,7 +289,7 @@
 #define CFG_I2C_SPEED		100000	/* I2C speed and slave address */
 #define CFG_I2C_SLAVE		0x7F
 #if 0
-#define CFG_I2C_NOPROBES	{{0,0x69}}	* Don't probe these addrs */
+#define CFG_I2C_NOPROBES	{{0,0x69}}	/* Don't probe these addrs */
 #endif
 
 /*
@@ -249,14 +307,14 @@
 #define CONFIG_NET_MULTI
 #define CONFIG_PHY_ADDR		0x1
 #define CONFIG_MII		1	/* MII PHY management		*/
+#define CONFIG_FEC_AN_TIMEOUT	1
+#define CONFIG_HAS_ETH0
 
-#if 0
 /*
  * Configure on-board RTC
  */
-#define CONFIG_RTC_DS1374			/* use ds1374 rtc via i2c	*/
+#define CONFIG_RTC_M41T62			/* use M41T62 rtc via i2 */
 #define CFG_I2C_RTC_ADDR		0x68	/* at address 0x68		*/
-#endif
 
 /*
  * Environment
@@ -265,7 +323,11 @@
 /* This has to be a multiple of the Flash sector size */
 #define CFG_ENV_ADDR		(CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 #define CFG_ENV_SIZE		0x2000
+#ifdef CONFIG_BKUP_FLASH
+#define CFG_ENV_SECT_SIZE	0x20000	/* one sector (256K) for env */
+#else
 #define CFG_ENV_SECT_SIZE	0x40000	/* one sector (256K) for env */
+#endif
 
 /* Address and size of Redundant Environment Sector	*/
 #define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
@@ -284,6 +346,7 @@
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_REGINFO
 #define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_DATE
 
 #if defined(CONFIG_PCI)
 #define CONFIG_CMD_PCI
@@ -295,7 +358,7 @@
  * to 0xFFFF, watchdog timeouts after about 64s. For details refer
  * to chapter 36 of the MPC5121e Reference Manual.
  */
-#define CONFIG_WATCHDOG			/* enable watchdog */
+/* #define CONFIG_WATCHDOG */		/* enable watchdog */
 #define CFG_WATCHDOG_VALUE 0xFFFF
 
  /*
@@ -306,9 +369,9 @@
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
 
 #ifdef CONFIG_CMD_KGDB
-	#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
+	#define CFG_CBSIZE	1024	/* Console I/O Buffer Size */
 #else
-	#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
+	#define CFG_CBSIZE	256	/* Console I/O Buffer Size */
 #endif
 
 
@@ -335,13 +398,15 @@
 #define CFG_HID0_FINAL	HID0_ENABLE_MACHINE_CHECK
 #define CFG_HID2	HID2_HBE
 
+#define CONFIG_HIGH_BATS	1	/* High BATs supported */
+
 /*
  * Internal Definitions
  *
  * Boot Flags
  */
-#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM	0x02	/* Software reboot */
+#define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH */
+#define BOOTFLAG_WARM		0x02	/* Software reboot */
 
 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
@@ -351,12 +416,13 @@
 /*
  * Environment Configuration
  */
-#define CONFIG_ENV_OVERWRITE
+#define CONFIG_TIMESTAMP
 
 #define CONFIG_HOSTNAME		ads5121
-#define CONFIG_BOOTFILE		uImage
+#define CONFIG_BOOTFILE		ads5121/uImage
+#define CONFIG_ROOTPATH		/opt/eldk/pcc_6xx
 
-#define CONFIG_LOADADDR		200000	/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		400000	/* default location for tftp and bootm */
 
 #define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */
 #undef  CONFIG_BOOTARGS			/* the boot command will set bootargs */
@@ -364,47 +430,60 @@
 #define CONFIG_BAUDRATE		115200
 
 #define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 	"echo"
 
 #define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"u-boot_addr_r=200000\0"					\
+	"kernel_addr_r=300000\0"					\
+	"fdt_addr_r=400000\0"						\
+	"ramdisk_addr_r=500000\0"					\
+	"u-boot_addr=FFF00000\0"					\
+	"kernel_addr=FC040000\0"					\
+	"fdt_addr=FC2C0000\0"						\
+	"ramdisk_addr=FC300000\0"					\
+	"ramdiskfile=ads5121/uRamdisk\0"				\
+	"fdtfile=ads5121/ads5121.dtb\0"					\
+	"u-boot=ads5121/u-boot.bin\0"					\
 	"netdev=eth0\0"							\
+	"consdev=ttyPSC0\0"						\
 	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
 		"nfsroot=${serverip}:${rootpath}\0"			\
 	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
 	"addip=setenv bootargs ${bootargs} "				\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
 		":${hostname}:${netdev}:off panic=1\0"			\
-	"addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
+	"addtty=setenv bootargs ${bootargs} "				\
+		"console=${consdev},${baudrate}\0"			\
 	"flash_nfs=run nfsargs addip addtty;"				\
-		"bootm ${kernel_addr}\0"				\
+		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
 	"flash_self=run ramargs addip addtty;"				\
-		"bootm ${kernel_addr} ${ramdisk_addr}\0"		\
-	"net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"	\
-		"bootm\0"						\
-	"load=tftp 200000 /tftpboot/ads5121/u-boot.bin\0"		\
-	"update=protect off FFF00000 +${filesize};"			\
-		"era FFF00000 +${filesize};cp.b 200000 FFF00000 ${filesize}\0" \
-	"upd=run load;run update\0"					\
+		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
+	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run nfsargs addip addtty;"				\
+		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
+	"net_self=tftp ${kernel_addr_r} ${bootfile};"			\
+		"tftp ${ramdisk_addr_r} ${ramdiskfile};"		\
+		"tftp ${fdt_addr_r} ${fdtfile};"			\
+		"run ramargs addip addtty;"				\
+		"bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
+	"load=tftp ${u-boot_addr_r} ${u-boot}\0"			\
+	"update=protect off ${u-boot_addr} +${filesize};"		\
+		"era ${u-boot_addr} +${filesize};"			\
+		"cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"	\
+	"upd=run load update\0"						\
 	""
 
-#define CONFIG_NFSBOOTCOMMAND						\
-	"setenv bootargs root=/dev/nfs rw "				\
-		"nfsroot=$serverip:$rootpath "				\
-		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
-		"console=$consoledev,$baudrate $othbootargs;"		\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr - $fdtaddr"
-
-#define CONFIG_RAMBOOTCOMMAND						\
-	"setenv bootargs root=/dev/ram rw "				\
-		"console=$consoledev,$baudrate $othbootargs;"		\
-	"tftp $ramdiskaddr $ramdiskfile;"				\
-	"tftp $loadaddr $bootfile;"					\
-	"tftp $fdtaddr $fdtfile;"					\
-	"bootm $loadaddr $ramdiskaddr $fdtaddr"
-
 #define CONFIG_BOOTCOMMAND	"run flash_self"
 
+#define CONFIG_OF_LIBFDT	1
+#define CONFIG_OF_BOARD_SETUP	1
+#define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES	1
+
+#define OF_CPU			"PowerPC,5121@0"
+#define OF_SOC_COMPAT		"fsl,mpc5121-immr"
+#define OF_TBCLK		(bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH		"/soc@80000000/serial@11300"
+
 #endif	/* __CONFIG_H */