X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;ds=sidebyside;f=include%2Fconfigs%2FM5249EVB.h;h=33ac2859dfb17afb20377b5230150c5757444b60;hb=26a33504a55e4882520f2e9da96ba6c22badb353;hp=8699ef98ee12a96f2f5c52301dbbb4422fc61d2e;hpb=6d0f6bcf337c5261c08fabe12982178c2c489d76;p=oweals%2Fu-boot.git

diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h
index 8699ef98ee..33ac2859df 100644
--- a/include/configs/M5249EVB.h
+++ b/include/configs/M5249EVB.h
@@ -60,6 +60,7 @@
  * Command line configuration.
  */
 #include <config_cmd_default.h>
+#define CONFIG_CMD_CACHE
 #undef CONFIG_CMD_NET
 
 #define CONFIG_SYS_PROMPT		"=> "
@@ -125,7 +126,7 @@
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000
 #define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */
-#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CSAR0 << 16)
+#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
 
 #if 0 /* test-only */
 #define CONFIG_PRAM		512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */
@@ -165,20 +166,34 @@
  */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 
+#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 8)
+#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
+					 CONFIG_SYS_INIT_RAM_END - 4)
+#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
+#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
+					 CF_ADDRMASK(2) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
+					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
+					 CF_ACR_EN | CF_ACR_SM_ALL)
+#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
+					 CF_CACR_DBWE)
+
 /*-----------------------------------------------------------------------
  * Memory bank definitions
  */
 
 /* CS0 - AMD Flash, address 0xffc00000 */
-#define	CONFIG_SYS_CSAR0		0xffe0
-#define	CONFIG_SYS_CSCR0		0x1980		/* WS=0110, AA=1, PS=10         */
+#define	CONFIG_SYS_CS0_BASE		0xffe00000
+#define	CONFIG_SYS_CS0_CTRL		0x00001980	/* WS=0110, AA=1, PS=10         */
 /** Note: There is a CSMR0/DRAM vector problem, need to disable C/I ***/
-#define	CONFIG_SYS_CSMR0		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */
+#define	CONFIG_SYS_CS0_MASK		0x003f0021	/* 4MB, AA=0, WP=0, C/I=1, V=1  */
 
 /* CS1 - FPGA, address 0xe0000000 */
-#define	CONFIG_SYS_CSAR1		0xe000
-#define	CONFIG_SYS_CSCR1		0x0d80		/* WS=0011, AA=1, PS=10         */
-#define	CONFIG_SYS_CSMR1		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/
+#define	CONFIG_SYS_CS1_BASE		0xe0000000
+#define	CONFIG_SYS_CS1_CTRL		0x00000d80	/* WS=0011, AA=1, PS=10         */
+#define	CONFIG_SYS_CS1_MASK		0x00010001	/* 128kB, AA=0, WP=0, C/I=0, V=1*/
 
 /*-----------------------------------------------------------------------
  * Port configuration