X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fsystemace.c;h=7d82c27c6edd7d35c9b15fc3ec6f62dce4f035bb;hb=fc9970137c8f187b5938e4926224e0f3d46c3476;hp=1d1be12520295f0094594eab200935e25e0a9524;hpb=da04995c7dc6772013a9a0dc5c767f190c402478;p=oweals%2Fu-boot.git diff --git a/drivers/systemace.c b/drivers/systemace.c index 1d1be12520..7d82c27c6e 100644 --- a/drivers/systemace.c +++ b/drivers/systemace.c @@ -56,12 +56,12 @@ #if (CFG_SYSTEMACE_WIDTH == 8) #if !defined(__BIG_ENDIAN) #define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)<<8) | \ - (readb(CFG_SYSTEMACE_BASE+off+1))) + (readb(CFG_SYSTEMACE_BASE+off+1))) #define ace_writew(val, off) {writeb(val>>8, CFG_SYSTEMACE_BASE+off); \ writeb(val, CFG_SYSTEMACE_BASE+off+1);} #else #define ace_readw(off) ((readb(CFG_SYSTEMACE_BASE+off)) | \ - (readb(CFG_SYSTEMACE_BASE+off+1)<<8)) + (readb(CFG_SYSTEMACE_BASE+off+1)<<8)) #define ace_writew(val, off) {writeb(val, CFG_SYSTEMACE_BASE+off); \ writeb(val>>8, CFG_SYSTEMACE_BASE+off+1);} #endif @@ -73,7 +73,7 @@ /* */ static unsigned long systemace_read(int dev, unsigned long start, - unsigned long blkcnt, void *buffer); + unsigned long blkcnt, void *buffer); static block_dev_desc_t systemace_dev = { 0 }; @@ -119,13 +119,10 @@ block_dev_desc_t *systemace_get_dev(int dev) systemace_dev.removable = 1; systemace_dev.block_read = systemace_read; -#if (CFG_SYSTEMACE_WIDTH == 16) /* - * By default the SystemACE comes up in 8-bit mode. - * Ensure that 16-bit mode gets enabled. + * Ensure the correct bus mode (8/16 bits) gets enabled */ - ace_writew(0x0001, 0); -#endif + ace_writew(CFG_SYSTEMACE_WIDTH == 8 ? 0 : 0x0001, 0); init_part(&systemace_dev); @@ -140,7 +137,7 @@ block_dev_desc_t *systemace_get_dev(int dev) * number of blocks read. A zero return indicates an error. */ static unsigned long systemace_read(int dev, unsigned long start, - unsigned long blkcnt, void *buffer) + unsigned long blkcnt, void *buffer) { int retry; unsigned blk_countdown; @@ -214,10 +211,16 @@ static unsigned long systemace_read(int dev, unsigned long start, /* Write sector count | ReadMemCardData. */ ace_writew((trans & 0xff) | 0x0300, 0x14); +/* + * For FPGA configuration via SystemACE is reset unacceptable + * CFGDONE bit in STATUSREG is not set to 1. + */ +#ifndef SYSTEMACE_CONFIG_FPGA /* Reset the configruation controller */ val = ace_readw(0x18); val |= 0x0080; ace_writew(val, 0x18); +#endif retry = trans * 16; while (retry > 0) {