X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fnet%2Fzynq_gem.c;h=1390c36c6141c610a47dfddd2e0e1164dad5888f;hb=f23b208ebe6a8e241b3801ccfbb2c49e680fad9b;hp=7059c8432a34959a2cc5a8caba230d9ac46e72fc;hpb=7bccc75a2b3f728981920abde4454ba4ea4e481a;p=oweals%2Fu-boot.git diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c index 7059c8432a..1390c36c61 100644 --- a/drivers/net/zynq_gem.c +++ b/drivers/net/zynq_gem.c @@ -9,6 +9,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ +#include #include #include #include @@ -19,11 +20,12 @@ #include #include #include +#include #include #include #include #include -#include +#include DECLARE_GLOBAL_DATA_PTR; @@ -52,11 +54,17 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_GEM_NWCTRL_MDEN_MASK 0x00000010 /* Enable MDIO port */ #define ZYNQ_GEM_NWCTRL_STARTTX_MASK 0x00000200 /* Start tx (tx_go) */ -#define ZYNQ_GEM_NWCFG_SPEED100 0x000000001 /* 100 Mbps operation */ -#define ZYNQ_GEM_NWCFG_SPEED1000 0x000000400 /* 1Gbps operation */ -#define ZYNQ_GEM_NWCFG_FDEN 0x000000002 /* Full Duplex mode */ -#define ZYNQ_GEM_NWCFG_FSREM 0x000020000 /* FCS removal */ -#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x0000c0000 /* Div pclk by 48, max 120MHz */ +#define ZYNQ_GEM_NWCFG_SPEED100 0x00000001 /* 100 Mbps operation */ +#define ZYNQ_GEM_NWCFG_SPEED1000 0x00000400 /* 1Gbps operation */ +#define ZYNQ_GEM_NWCFG_FDEN 0x00000002 /* Full Duplex mode */ +#define ZYNQ_GEM_NWCFG_FSREM 0x00020000 /* FCS removal */ +#define ZYNQ_GEM_NWCFG_SGMII_ENBL 0x08000000 /* SGMII Enable */ +#define ZYNQ_GEM_NWCFG_PCS_SEL 0x00000800 /* PCS select */ +#ifdef CONFIG_ARM64 +#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x00100000 /* Div pclk by 64, max 160MHz */ +#else +#define ZYNQ_GEM_NWCFG_MDCCLKDIV 0x000c0000 /* Div pclk by 48, max 120MHz */ +#endif #ifdef CONFIG_ARM64 # define ZYNQ_GEM_DBUS_WIDTH (1 << 21) /* 64 bit bus */ @@ -86,6 +94,8 @@ DECLARE_GLOBAL_DATA_PTR; #define ZYNQ_GEM_TSR_DONE 0x00000020 /* Tx done mask */ +#define ZYNQ_GEM_PCS_CTL_ANEG_ENBL 0x1000 + /* Use MII register 1 (MII status register) to detect PHY */ #define PHY_DETECT_REG 1 @@ -132,7 +142,9 @@ struct zynq_gem_regs { u32 reserved6[18]; #define STAT_SIZE 44 u32 stat[STAT_SIZE]; /* 0x100 - Octects transmitted Low reg */ - u32 reserved7[164]; + u32 reserved9[20]; + u32 pcscntrl; + u32 reserved7[143]; u32 transmit_q1_ptr; /* 0x440 - Transmit priority queue 1 */ u32 reserved8[15]; u32 receive_q1_ptr; /* 0x480 - Receive priority queue 1 */ @@ -163,41 +175,27 @@ struct zynq_gem_priv { u32 rxbd_current; u32 rx_first_buf; int phyaddr; - u32 emio; int init; struct zynq_gem_regs *iobase; phy_interface_t interface; struct phy_device *phydev; + int phy_of_handle; struct mii_dev *bus; + struct clk clk; + bool int_pcs; }; -static inline int mdio_wait(struct zynq_gem_regs *regs) -{ - u32 timeout = 20000; - - /* Wait till MDIO interface is ready to accept a new transaction. */ - while (--timeout) { - if (readl(®s->nwsr) & ZYNQ_GEM_NWSR_MDIOIDLE_MASK) - break; - WATCHDOG_RESET(); - } - - if (!timeout) { - printf("%s: Timeout\n", __func__); - return 1; - } - - return 0; -} - static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, u32 op, u16 *data) { u32 mgtcr; struct zynq_gem_regs *regs = priv->iobase; + int err; - if (mdio_wait(regs)) - return 1; + err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, + true, 20000, false); + if (err) + return err; /* Construct mgtcr mask for the operation */ mgtcr = ZYNQ_GEM_PHYMNTNC_OP_MASK | op | @@ -207,8 +205,10 @@ static u32 phy_setup_op(struct zynq_gem_priv *priv, u32 phy_addr, u32 regnum, /* Write mgtcr and wait for completion */ writel(mgtcr, ®s->phymntnc); - if (mdio_wait(regs)) - return 1; + err = wait_for_bit_le32(®s->nwsr, ZYNQ_GEM_NWSR_MDIOIDLE_MASK, + true, 20000, false); + if (err) + return err; if (op == ZYNQ_GEM_PHYMNTNC_OP_R_MASK) *data = readl(®s->phymntnc); @@ -325,10 +325,13 @@ static int zynq_phy_init(struct udevice *dev) /* Enable only MDIO bus */ writel(ZYNQ_GEM_NWCTRL_MDEN_MASK, ®s->nwctrl); - ret = phy_detection(dev); - if (ret) { - printf("GEM PHY init failed\n"); - return ret; + if ((priv->interface != PHY_INTERFACE_MODE_SGMII) && + (priv->interface != PHY_INTERFACE_MODE_GMII)) { + ret = phy_detection(dev); + if (ret) { + printf("GEM PHY init failed\n"); + return ret; + } } priv->phydev = phy_connect(priv->bus, priv->phyaddr, dev, @@ -336,17 +339,20 @@ static int zynq_phy_init(struct udevice *dev) if (!priv->phydev) return -ENODEV; - priv->phydev->supported = supported | ADVERTISED_Pause | + priv->phydev->supported &= supported | ADVERTISED_Pause | ADVERTISED_Asym_Pause; priv->phydev->advertising = priv->phydev->supported; - phy_config(priv->phydev); - return 0; + if (priv->phy_of_handle > 0) + dev_set_of_offset(priv->phydev->dev, priv->phy_of_handle); + + return phy_config(priv->phydev); } static int zynq_gem_init(struct udevice *dev) { - u32 i; + u32 i, nwconfig; + int ret; unsigned long clk_rate = 0; struct zynq_gem_priv *priv = dev_get_priv(dev); struct zynq_gem_regs *regs = priv->iobase; @@ -403,10 +409,6 @@ static int zynq_gem_init(struct udevice *dev) dummy_rx_bd->addr = ZYNQ_GEM_RXBUF_WRAP_MASK | ZYNQ_GEM_RXBUF_NEW_MASK; dummy_rx_bd->status = 0; - flush_dcache_range((ulong)&dummy_tx_bd, (ulong)&dummy_tx_bd + - sizeof(dummy_tx_bd)); - flush_dcache_range((ulong)&dummy_rx_bd, (ulong)&dummy_rx_bd + - sizeof(dummy_rx_bd)); writel((ulong)dummy_tx_bd, ®s->transmit_q1_ptr); writel((ulong)dummy_rx_bd, ®s->receive_q1_ptr); @@ -414,21 +416,39 @@ static int zynq_gem_init(struct udevice *dev) priv->init++; } - phy_startup(priv->phydev); + ret = phy_startup(priv->phydev); + if (ret) + return ret; if (!priv->phydev->link) { printf("%s: No link.\n", priv->phydev->dev->name); return -1; } + nwconfig = ZYNQ_GEM_NWCFG_INIT; + + /* + * Set SGMII enable PCS selection only if internal PCS/PMA + * core is used and interface is SGMII. + */ + if (priv->interface == PHY_INTERFACE_MODE_SGMII && + priv->int_pcs) { + nwconfig |= ZYNQ_GEM_NWCFG_SGMII_ENBL | + ZYNQ_GEM_NWCFG_PCS_SEL; +#ifdef CONFIG_ARM64 + writel(readl(®s->pcscntrl) | ZYNQ_GEM_PCS_CTL_ANEG_ENBL, + ®s->pcscntrl); +#endif + } + switch (priv->phydev->speed) { case SPEED_1000: - writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED1000, + writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED1000, ®s->nwcfg); clk_rate = ZYNQ_GEM_FREQUENCY_1000; break; case SPEED_100: - writel(ZYNQ_GEM_NWCFG_INIT | ZYNQ_GEM_NWCFG_SPEED100, + writel(nwconfig | ZYNQ_GEM_NWCFG_SPEED100, ®s->nwcfg); clk_rate = ZYNQ_GEM_FREQUENCY_100; break; @@ -437,10 +457,17 @@ static int zynq_gem_init(struct udevice *dev) break; } - /* Change the rclk and clk only not using EMIO interface */ - if (!priv->emio) - zynq_slcr_gem_clk_setup((ulong)priv->iobase != - ZYNQ_GEM_BASEADDR0, clk_rate); + ret = clk_set_rate(&priv->clk, clk_rate); + if (IS_ERR_VALUE(ret) && ret != (unsigned long)-ENOSYS) { + dev_err(dev, "failed to set tx clock rate\n"); + return ret; + } + + ret = clk_enable(&priv->clk); + if (ret && ret != -ENOSYS) { + dev_err(dev, "failed to enable tx clock\n"); + return ret; + } setbits_le32(®s->nwctrl, ZYNQ_GEM_NWCTRL_RXEN_MASK | ZYNQ_GEM_NWCTRL_TXEN_MASK); @@ -448,38 +475,6 @@ static int zynq_gem_init(struct udevice *dev) return 0; } -static int wait_for_bit(const char *func, u32 *reg, const u32 mask, - bool set, unsigned int timeout) -{ - u32 val; - unsigned long start = get_timer(0); - - while (1) { - val = readl(reg); - - if (!set) - val = ~val; - - if ((val & mask) == mask) - return 0; - - if (get_timer(start) > timeout) - break; - - if (ctrlc()) { - puts("Abort\n"); - return -EINTR; - } - - udelay(1); - } - - debug("%s: Timeout (reg=%p mask=%08x wait_set=%i)\n", - func, reg, mask, set); - - return -ETIMEDOUT; -} - static int zynq_gem_send(struct udevice *dev, void *ptr, int len) { u32 addr, size; @@ -520,8 +515,8 @@ static int zynq_gem_send(struct udevice *dev, void *ptr, int len) if (priv->tx_bd->status & ZYNQ_GEM_TXBUF_EXHAUSTED) printf("TX buffers exhausted in mid frame\n"); - return wait_for_bit(__func__, ®s->txsr, ZYNQ_GEM_TSR_DONE, - true, 20000); + return wait_for_bit_le32(®s->txsr, ZYNQ_GEM_TSR_DONE, + true, 20000, true); } /* Do not check frame_recd flag in rx_status register 0x20 - just poll BD */ @@ -588,6 +583,21 @@ static void zynq_gem_halt(struct udevice *dev) ZYNQ_GEM_NWCTRL_TXEN_MASK, 0); } +__weak int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) +{ + return -ENOSYS; +} + +static int zynq_gem_read_rom_mac(struct udevice *dev) +{ + struct eth_pdata *pdata = dev_get_platdata(dev); + + if (!pdata) + return -ENOSYS; + + return zynq_board_read_rom_ethaddr(pdata->enetaddr); +} + static int zynq_gem_miiphy_read(struct mii_dev *bus, int addr, int devad, int reg) { @@ -628,19 +638,22 @@ static int zynq_gem_probe(struct udevice *dev) priv->tx_bd = (struct emac_bd *)bd_space; priv->rx_bd = (struct emac_bd *)((ulong)bd_space + BD_SEPRN_SPACE); + ret = clk_get_by_name(dev, "tx_clk", &priv->clk); + if (ret < 0) { + dev_err(dev, "failed to get clock\n"); + return -EINVAL; + } + priv->bus = mdio_alloc(); priv->bus->read = zynq_gem_miiphy_read; priv->bus->write = zynq_gem_miiphy_write; priv->bus->priv = priv; - strcpy(priv->bus->name, "gem"); - ret = mdio_register(priv->bus); + ret = mdio_register_seq(priv->bus, dev->seq); if (ret) return ret; - zynq_phy_init(dev); - - return 0; + return zynq_phy_init(dev); } static int zynq_gem_remove(struct udevice *dev) @@ -661,27 +674,28 @@ static const struct eth_ops zynq_gem_ops = { .free_pkt = zynq_gem_free_pkt, .stop = zynq_gem_halt, .write_hwaddr = zynq_gem_setup_mac, + .read_rom_hwaddr = zynq_gem_read_rom_mac, }; static int zynq_gem_ofdata_to_platdata(struct udevice *dev) { struct eth_pdata *pdata = dev_get_platdata(dev); struct zynq_gem_priv *priv = dev_get_priv(dev); - int offset = 0; + int node = dev_of_offset(dev); const char *phy_mode; - pdata->iobase = (phys_addr_t)dev_get_addr(dev); + pdata->iobase = (phys_addr_t)devfdt_get_addr(dev); priv->iobase = (struct zynq_gem_regs *)pdata->iobase; /* Hardcode for now */ - priv->emio = 0; priv->phyaddr = -1; - offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, - "phy-handle"); - if (offset > 0) - priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); + priv->phy_of_handle = fdtdec_lookup_phandle(gd->fdt_blob, node, + "phy-handle"); + if (priv->phy_of_handle > 0) + priv->phyaddr = fdtdec_get_int(gd->fdt_blob, + priv->phy_of_handle, "reg", -1); - phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); + phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); if (phy_mode) pdata->phy_interface = phy_get_interface_by_name(phy_mode); if (pdata->phy_interface == -1) { @@ -690,7 +704,10 @@ static int zynq_gem_ofdata_to_platdata(struct udevice *dev) } priv->interface = pdata->phy_interface; - printf("ZYNQ GEM: %lx, phyaddr %d, interface %s\n", (ulong)priv->iobase, + priv->int_pcs = fdtdec_get_bool(gd->fdt_blob, node, + "is-internal-pcspma"); + + printf("ZYNQ GEM: %lx, phyaddr %x, interface %s\n", (ulong)priv->iobase, priv->phyaddr, phy_string_for_interface(priv->interface)); return 0;