X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fnet%2Fphy%2Fmarvell.c;h=be5e3dcaab20fb831e0740e164e739daab5c7262;hb=c05ed00afb95fa5237f16962fccf5810437317bf;hp=b8b1157a0a4a19c9307bdf6a53135195407e08dd;hpb=cf432dd5953e9ddf06759565c80fed470882da6d;p=oweals%2Fu-boot.git diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c index b8b1157a0a..be5e3dcaab 100644 --- a/drivers/net/phy/marvell.c +++ b/drivers/net/phy/marvell.c @@ -1,17 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Marvell PHY drivers * - * SPDX-License-Identifier: GPL-2.0+ - * * Copyright 2010-2011 Freescale Semiconductor, Inc. * author Andy Fleming */ -#include #include +#include #include +#include #define PHY_AUTONEGOTIATE_TIMEOUT 5000 +#define MII_MARVELL_PHY_PAGE 22 + /* 88E1011 PHY Status Register */ #define MIIM_88E1xxx_PHY_STATUS 0x11 #define MIIM_88E1xxx_PHYSTAT_SPEED 0xc000 @@ -81,6 +83,51 @@ #define MIIM_88E1310_PHY_RGMII_CTRL 21 #define MIIM_88E1310_PHY_PAGE 22 +/* 88E151x PHY defines */ +/* Page 2 registers */ +#define MIIM_88E151x_PHY_MSCR 21 +#define MIIM_88E151x_RGMII_RX_DELAY BIT(5) +#define MIIM_88E151x_RGMII_TX_DELAY BIT(4) +#define MIIM_88E151x_RGMII_RXTX_DELAY (BIT(5) | BIT(4)) +/* Page 3 registers */ +#define MIIM_88E151x_LED_FUNC_CTRL 16 +#define MIIM_88E151x_LED_FLD_SZ 4 +#define MIIM_88E151x_LED0_OFFS (0 * MIIM_88E151x_LED_FLD_SZ) +#define MIIM_88E151x_LED1_OFFS (1 * MIIM_88E151x_LED_FLD_SZ) +#define MIIM_88E151x_LED0_ACT 3 +#define MIIM_88E151x_LED1_100_1000_LINK 6 +#define MIIM_88E151x_LED_TIMER_CTRL 18 +#define MIIM_88E151x_INT_EN_OFFS 7 +/* Page 18 registers */ +#define MIIM_88E151x_GENERAL_CTRL 20 +#define MIIM_88E151x_MODE_SGMII 1 +#define MIIM_88E151x_RESET_OFFS 15 + +static int m88e1xxx_phy_extread(struct phy_device *phydev, int addr, + int devaddr, int regnum) +{ + int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); + int val; + + phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr); + val = phy_read(phydev, MDIO_DEVAD_NONE, regnum); + phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage); + + return val; +} + +static int m88e1xxx_phy_extwrite(struct phy_device *phydev, int addr, + int devaddr, int regnum, u16 val) +{ + int oldpage = phy_read(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE); + + phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, devaddr); + phy_write(phydev, MDIO_DEVAD_NONE, regnum, val); + phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, oldpage); + + return 0; +} + /* Marvell 88E1011S */ static int m88e1011s_config(struct phy_device *phydev) { @@ -103,7 +150,7 @@ static int m88e1011s_config(struct phy_device *phydev) /* Parse the 88E1011's status register for speed and duplex * information */ -static uint m88e1xxx_parse_status(struct phy_device *phydev) +static int m88e1xxx_parse_status(struct phy_device *phydev) { unsigned int speed; unsigned int mii_reg; @@ -111,7 +158,7 @@ static uint m88e1xxx_parse_status(struct phy_device *phydev) mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_STATUS); if ((mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) && - !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { + !(mii_reg & MIIM_88E1xxx_PHYSTAT_SPDDONE)) { int i = 0; puts("Waiting for PHY realtime link"); @@ -120,17 +167,17 @@ static uint m88e1xxx_parse_status(struct phy_device *phydev) if (i > PHY_AUTONEGOTIATE_TIMEOUT) { puts(" TIMEOUT !\n"); phydev->link = 0; - break; + return -ETIMEDOUT; } if ((i++ % 1000) == 0) putc('.'); udelay(1000); mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, - MIIM_88E1xxx_PHY_STATUS); + MIIM_88E1xxx_PHY_STATUS); } puts(" done\n"); - udelay(500000); /* another 500 ms (results in faster booting) */ + mdelay(500); /* another 500 ms (results in faster booting) */ } else { if (mii_reg & MIIM_88E1xxx_PHYSTAT_LINK) phydev->link = 1; @@ -162,10 +209,13 @@ static uint m88e1xxx_parse_status(struct phy_device *phydev) static int m88e1011s_startup(struct phy_device *phydev) { - genphy_update_link(phydev); - m88e1xxx_parse_status(phydev); + int ret; - return 0; + ret = genphy_update_link(phydev); + if (ret) + return ret; + + return m88e1xxx_parse_status(phydev); } /* Marvell 88E1111S */ @@ -173,14 +223,11 @@ static int m88e1111s_config(struct phy_device *phydev) { int reg; - if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || - (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || - (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) || - (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { + if (phy_interface_is_rgmii(phydev)) { reg = phy_read(phydev, - MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR); + MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR); if ((phydev->interface == PHY_INTERFACE_MODE_RGMII) || - (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) { + (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)) { reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); } else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) { reg &= ~MIIM_88E1111_TX_DELAY; @@ -191,10 +238,10 @@ static int m88e1111s_config(struct phy_device *phydev) } phy_write(phydev, - MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg); + MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg); reg = phy_read(phydev, - MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR); + MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR); reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); @@ -204,47 +251,47 @@ static int m88e1111s_config(struct phy_device *phydev) reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RGMII; phy_write(phydev, - MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg); + MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR, reg); } if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { reg = phy_read(phydev, - MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR); + MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_SR); reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK; reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; phy_write(phydev, MDIO_DEVAD_NONE, - MIIM_88E1111_PHY_EXT_SR, reg); + MIIM_88E1111_PHY_EXT_SR, reg); } if (phydev->interface == PHY_INTERFACE_MODE_RTBI) { reg = phy_read(phydev, - MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR); + MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR); reg |= (MIIM_88E1111_RX_DELAY | MIIM_88E1111_TX_DELAY); phy_write(phydev, - MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg); + MDIO_DEVAD_NONE, MIIM_88E1111_PHY_EXT_CR, reg); reg = phy_read(phydev, MDIO_DEVAD_NONE, - MIIM_88E1111_PHY_EXT_SR); + MIIM_88E1111_PHY_EXT_SR); reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | MIIM_88E1111_HWCFG_FIBER_COPPER_RES); reg |= 0x7 | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; phy_write(phydev, MDIO_DEVAD_NONE, - MIIM_88E1111_PHY_EXT_SR, reg); + MIIM_88E1111_PHY_EXT_SR, reg); /* soft reset */ phy_reset(phydev); reg = phy_read(phydev, MDIO_DEVAD_NONE, - MIIM_88E1111_PHY_EXT_SR); + MIIM_88E1111_PHY_EXT_SR); reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK | - MIIM_88E1111_HWCFG_FIBER_COPPER_RES); + MIIM_88E1111_HWCFG_FIBER_COPPER_RES); reg |= MIIM_88E1111_HWCFG_MODE_COPPER_RTBI | MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; phy_write(phydev, MDIO_DEVAD_NONE, - MIIM_88E1111_PHY_EXT_SR, reg); + MIIM_88E1111_PHY_EXT_SR, reg); } /* soft reset */ @@ -257,10 +304,10 @@ static int m88e1111s_config(struct phy_device *phydev) } /** - * m88e1518_phy_writebits - write bits to a register + * m88e151x_phy_writebits - write bits to a register */ -void m88e1518_phy_writebits(struct phy_device *phydev, - u8 reg_num, u16 offset, u16 len, u16 data) +void m88e151x_phy_writebits(struct phy_device *phydev, + u8 reg_num, u16 offset, u16 len, u16 data) { u16 reg, mask; @@ -277,15 +324,17 @@ void m88e1518_phy_writebits(struct phy_device *phydev, phy_write(phydev, MDIO_DEVAD_NONE, reg_num, reg); } -static int m88e1518_config(struct phy_device *phydev) +static int m88e151x_config(struct phy_device *phydev) { + u16 reg; + /* * As per Marvell Release Notes - Alaska 88E1510/88E1518/88E1512 * /88E1514 Rev A0, Errata Section 3.1 */ /* EEE initialization */ - phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00ff); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff); phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x214B); phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2144); phy_write(phydev, MDIO_DEVAD_NONE, 17, 0x0C28); @@ -294,45 +343,63 @@ static int m88e1518_config(struct phy_device *phydev) phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x214D); phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xCC0C); phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x2159); - phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x0000); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); /* SGMII-to-Copper mode initialization */ if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { /* Select page 18 */ - phy_write(phydev, MDIO_DEVAD_NONE, 22, 18); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 18); /* In reg 20, write MODE[2:0] = 0x1 (SGMII to Copper) */ - m88e1518_phy_writebits(phydev, 20, 0, 3, 1); + m88e151x_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL, + 0, 3, MIIM_88E151x_MODE_SGMII); /* PHY reset is necessary after changing MODE[2:0] */ - m88e1518_phy_writebits(phydev, 20, 15, 1, 1); + m88e151x_phy_writebits(phydev, MIIM_88E151x_GENERAL_CTRL, + MIIM_88E151x_RESET_OFFS, 1, 1); /* Reset page selection */ - phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0); udelay(100); } - return m88e1111s_config(phydev); -} + if (phydev->interface == PHY_INTERFACE_MODE_SGMII) { + reg = phy_read(phydev, MDIO_DEVAD_NONE, + MIIM_88E1111_PHY_EXT_SR); -/* Marvell 88E1510 */ -static int m88e1510_config(struct phy_device *phydev) -{ - /* Select page 3 */ - phy_write(phydev, MDIO_DEVAD_NONE, 22, 3); + reg &= ~(MIIM_88E1111_HWCFG_MODE_MASK); + reg |= MIIM_88E1111_HWCFG_MODE_SGMII_NO_CLK; + reg |= MIIM_88E1111_HWCFG_FIBER_COPPER_AUTO; + + phy_write(phydev, MDIO_DEVAD_NONE, + MIIM_88E1111_PHY_EXT_SR, reg); + } - /* Enable INTn output on LED[2] */ - m88e1518_phy_writebits(phydev, 18, 7, 1, 1); + if (phy_interface_is_rgmii(phydev)) { + phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 2); + + reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR); + reg &= ~MIIM_88E151x_RGMII_RXTX_DELAY; + if (phydev->interface == PHY_INTERFACE_MODE_RGMII || + phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) + reg |= MIIM_88E151x_RGMII_RXTX_DELAY; + else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) + reg |= MIIM_88E151x_RGMII_RX_DELAY; + else if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) + reg |= MIIM_88E151x_RGMII_TX_DELAY; + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E151x_PHY_MSCR, reg); + + phy_write(phydev, MDIO_DEVAD_NONE, MII_MARVELL_PHY_PAGE, 0); + } - /* Configure LEDs */ - m88e1518_phy_writebits(phydev, 16, 0, 4, 3); /* LED[0]:0011 (ACT) */ - m88e1518_phy_writebits(phydev, 16, 4, 4, 6); /* LED[1]:0110 (LINK) */ + /* soft reset */ + phy_reset(phydev); - /* Reset page selection */ - phy_write(phydev, MDIO_DEVAD_NONE, 22, 0); + genphy_config_aneg(phydev); + genphy_restart_aneg(phydev); - return m88e1518_config(phydev); + return 0; } /* Marvell 88E1118 */ @@ -349,22 +416,21 @@ static int m88e1118_config(struct phy_device *phydev) /* Change Page Number */ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); - genphy_config_aneg(phydev); - - phy_reset(phydev); - - return 0; + return genphy_config_aneg(phydev); } static int m88e1118_startup(struct phy_device *phydev) { + int ret; + /* Change Page Number */ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); - genphy_update_link(phydev); - m88e1xxx_parse_status(phydev); + ret = genphy_update_link(phydev); + if (ret) + return ret; - return 0; + return m88e1xxx_parse_status(phydev); } /* Marvell 88E1121R */ @@ -378,10 +444,10 @@ static int m88e1121_config(struct phy_device *phydev) /* Switch the page to access the led register */ pg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE); phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, - MIIM_88E1121_PHY_LED_PAGE); + MIIM_88E1121_PHY_LED_PAGE); /* Configure leds */ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_LED_CTRL, - MIIM_88E1121_PHY_LED_DEF); + MIIM_88E1121_PHY_LED_DEF); /* Restore the page pointer */ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1121_PHY_PAGE, pg); @@ -404,7 +470,7 @@ static int m88e1145_config(struct phy_device *phydev) phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_CAL_OV, 0xa2da); phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1xxx_PHY_SCR, - MIIM_88E1xxx_PHY_MDI_X_AUTO); + MIIM_88E1xxx_PHY_MDI_X_AUTO); reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_EXT_CR); if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) @@ -414,19 +480,25 @@ static int m88e1145_config(struct phy_device *phydev) genphy_config_aneg(phydev); - phy_reset(phydev); + /* soft reset */ + reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + reg |= BMCR_RESET; + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); return 0; } static int m88e1145_startup(struct phy_device *phydev) { - genphy_update_link(phydev); - phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL, - MIIM_88E1145_PHY_LED_DIRECT); - m88e1xxx_parse_status(phydev); + int ret; - return 0; + ret = genphy_update_link(phydev); + if (ret) + return ret; + + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1145_PHY_LED_CONTROL, + MIIM_88E1145_PHY_LED_DIRECT); + return m88e1xxx_parse_status(phydev); } /* Marvell 88E1149S */ @@ -471,8 +543,48 @@ static int m88e1310_config(struct phy_device *phydev) /* Ensure to return to page 0 */ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0000); - genphy_config_aneg(phydev); - phy_reset(phydev); + return genphy_config_aneg(phydev); +} + +static int m88e1680_config(struct phy_device *phydev) +{ + /* + * As per Marvell Release Notes - Alaska V 88E1680 Rev A2 + * Errata Section 4.1 + */ + u16 reg; + int res; + + /* Matrix LED mode (not neede if single LED mode is used */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0004); + reg = phy_read(phydev, MDIO_DEVAD_NONE, 27); + reg |= (1 << 5); + phy_write(phydev, MDIO_DEVAD_NONE, 27, reg); + + /* QSGMII TX amplitude change */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00fd); + phy_write(phydev, MDIO_DEVAD_NONE, 8, 0x0b53); + phy_write(phydev, MDIO_DEVAD_NONE, 7, 0x200d); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); + + /* EEE initialization */ + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x00ff); + phy_write(phydev, MDIO_DEVAD_NONE, 17, 0xb030); + phy_write(phydev, MDIO_DEVAD_NONE, 16, 0x215c); + phy_write(phydev, MDIO_DEVAD_NONE, 22, 0x00fc); + phy_write(phydev, MDIO_DEVAD_NONE, 24, 0x888c); + phy_write(phydev, MDIO_DEVAD_NONE, 25, 0x888c); + phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1118_PHY_PAGE, 0x0000); + phy_write(phydev, MDIO_DEVAD_NONE, 0, 0x9140); + + res = genphy_config_aneg(phydev); + if (res < 0) + return res; + + /* soft reset */ + reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR); + reg |= BMCR_RESET; + phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg); return 0; } @@ -547,33 +659,35 @@ static struct phy_driver M88E1149S_driver = { .shutdown = &genphy_shutdown, }; -static struct phy_driver M88E1510_driver = { - .name = "Marvell 88E1510", +static struct phy_driver M88E151x_driver = { + .name = "Marvell 88E151x", .uid = 0x1410dd0, .mask = 0xffffff0, .features = PHY_GBIT_FEATURES, - .config = &m88e1510_config, + .config = &m88e151x_config, .startup = &m88e1011s_startup, .shutdown = &genphy_shutdown, + .readext = &m88e1xxx_phy_extread, + .writeext = &m88e1xxx_phy_extwrite, }; -static struct phy_driver M88E1518_driver = { - .name = "Marvell 88E1518", - .uid = 0x1410dd1, +static struct phy_driver M88E1310_driver = { + .name = "Marvell 88E1310", + .uid = 0x01410e90, .mask = 0xffffff0, .features = PHY_GBIT_FEATURES, - .config = &m88e1518_config, + .config = &m88e1310_config, .startup = &m88e1011s_startup, .shutdown = &genphy_shutdown, }; -static struct phy_driver M88E1310_driver = { - .name = "Marvell 88E1310", - .uid = 0x01410e90, +static struct phy_driver M88E1680_driver = { + .name = "Marvell 88E1680", + .uid = 0x1410ed0, .mask = 0xffffff0, .features = PHY_GBIT_FEATURES, - .config = &m88e1310_config, - .startup = &m88e1011s_startup, + .config = &m88e1680_config, + .startup = &genphy_startup, .shutdown = &genphy_shutdown, }; @@ -587,8 +701,8 @@ int phy_marvell_init(void) phy_register(&M88E1118R_driver); phy_register(&M88E1111S_driver); phy_register(&M88E1011S_driver); - phy_register(&M88E1510_driver); - phy_register(&M88E1518_driver); + phy_register(&M88E151x_driver); + phy_register(&M88E1680_driver); return 0; }