X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;ds=sidebyside;f=drivers%2Fnet%2Flpc32xx_eth.c;h=e76e9bc2b5bdee62116ac3246e5d04520115293c;hb=c8e29271b1a45ec87386857b506cfd918d9a4ad2;hp=6033392945c12806de358c1345ef63342670b5d5;hpb=fe0596cac3079a74eeee93e2940010a7a158c58d;p=oweals%2Fu-boot.git

diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c
index 6033392945..e76e9bc2b5 100644
--- a/drivers/net/lpc32xx_eth.c
+++ b/drivers/net/lpc32xx_eth.c
@@ -151,7 +151,7 @@ struct lpc32xx_eth_registers {
 #define SUPP_SPEED 0x00000100
 
 /* MCFG register bitfields/masks and offsets (see Table 292) */
-#define MCFG_CLOCK_SELECT_MASK  0x0000001C
+#define MCFG_RESET_MII_MGMT     0x00008000
 /* divide clock by 28 (see Table 293) */
 #define MCFG_CLOCK_SELECT_DIV28 0x0000001C
 
@@ -168,6 +168,7 @@ struct lpc32xx_eth_registers {
 #define COMMAND_RXENABLE      0x00000001
 #define COMMAND_TXENABLE      0x00000002
 #define COMMAND_PASSRUNTFRAME 0x00000040
+#define COMMAND_RMII          0x00000200
 #define COMMAND_FULL_DUPLEX   0x00000400
 /* Helper: general reset */
 #define COMMAND_RESETS        0x00000038
@@ -201,6 +202,7 @@ struct lpc32xx_eth_device {
 	struct eth_device dev;
 	struct lpc32xx_eth_registers *regs;
 	struct lpc32xx_eth_buffers *bufs;
+	bool phy_rmii;
 };
 
 #define LPC32XX_ETH_DEVICE_SIZE (sizeof(struct lpc32xx_eth_device))
@@ -351,15 +353,20 @@ int lpc32xx_eth_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
 #endif
 
 /*
+ * Provide default Ethernet buffers base address if target did not.
  * Locate buffers in SRAM at 0x00001000 to avoid cache issues and
  * maximize throughput.
  */
-
-#define LPC32XX_ETH_BUFS 0x00001000
+#if !defined(CONFIG_LPC32XX_ETH_BUFS_BASE)
+#define CONFIG_LPC32XX_ETH_BUFS_BASE 0x00001000
+#endif
 
 static struct lpc32xx_eth_device lpc32xx_eth = {
 	.regs = (struct lpc32xx_eth_registers *)LPC32XX_ETH_BASE,
-	.bufs = (struct lpc32xx_eth_buffers *)LPC32XX_ETH_BUFS
+	.bufs = (struct lpc32xx_eth_buffers *)CONFIG_LPC32XX_ETH_BUFS_BASE,
+#if defined(CONFIG_RMII)
+	.phy_rmii = true,
+#endif
 };
 
 #define TX_TIMEOUT 10000
@@ -459,8 +466,22 @@ static int lpc32xx_eth_init(struct eth_device *dev)
 	struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
 	int index;
 
-	/* Release SOFT reset to let MII talk to PHY */
-	clrbits_le32(&regs->mac1, MAC1_SOFT_RESET);
+	/* Initial MAC initialization */
+	writel(MAC1_PASS_ALL_RX_FRAMES, &regs->mac1);
+	writel(MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE, &regs->mac2);
+	writel(PKTSIZE_ALIGN, &regs->maxf);
+
+	/* Retries: 15 (0xF). Collision window: 57 (0x37). */
+	writel(0x370F, &regs->clrt);
+
+	/* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */
+	writel(0x0012, &regs->ipgr);
+
+	/* pass runt (smaller than 64 bytes) frames */
+	if (lpc32xx_eth_device->phy_rmii)
+		writel(COMMAND_PASSRUNTFRAME | COMMAND_RMII, &regs->command);
+	else
+		writel(COMMAND_PASSRUNTFRAME, &regs->command);
 
 	/* Configure Full/Half Duplex mode */
 	if (miiphy_duplex(dev->name, CONFIG_PHY_ADDR) == FULL) {
@@ -477,20 +498,6 @@ static int lpc32xx_eth_init(struct eth_device *dev)
 	else
 		writel(0, &regs->supp);
 
-	/* Initial MAC initialization */
-	writel(MAC1_PASS_ALL_RX_FRAMES, &regs->mac1);
-	writel(MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE, &regs->mac2);
-	writel(PKTSIZE_ALIGN, &regs->maxf);
-
-	/* Retries: 15 (0xF). Collision window: 57 (0x37). */
-	writel(0x370F, &regs->clrt);
-
-	/* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */
-	writel(0x0012, &regs->ipgr);
-
-	/* pass runt (smaller than 64 bytes) frames */
-	writel(COMMAND_PASSRUNTFRAME, &regs->command);
-
 	/* Save station address */
 	writel((unsigned long) (dev->enetaddr[0] |
 		(dev->enetaddr[1] << 8)), &regs->sa2);
@@ -562,6 +569,8 @@ static int lpc32xx_eth_halt(struct eth_device *dev)
 #if defined(CONFIG_PHYLIB)
 int lpc32xx_eth_phylib_init(struct eth_device *dev, int phyid)
 {
+	struct lpc32xx_eth_device *lpc32xx_eth_device =
+		container_of(dev, struct lpc32xx_eth_device, dev);
 	struct mii_dev *bus;
 	struct phy_device *phydev;
 	int ret;
@@ -582,7 +591,11 @@ int lpc32xx_eth_phylib_init(struct eth_device *dev, int phyid)
 		return -ENOMEM;
 	}
 
-	phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_MII);
+	if (lpc32xx_eth_device->phy_rmii)
+		phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RMII);
+	else
+		phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_MII);
+
 	if (!phydev) {
 		printf("phy_connect failed\n");
 		return -ENODEV;
@@ -604,7 +617,7 @@ int lpc32xx_eth_initialize(bd_t *bis)
 	 * Set RMII management clock rate. With HCLK at 104 MHz and
 	 * a divider of 28, this will be 3.72 MHz.
 	 */
-
+	writel(MCFG_RESET_MII_MGMT, &regs->mcfg);
 	writel(MCFG_CLOCK_SELECT_DIV28, &regs->mcfg);
 
 	/* Reset all MAC logic */