X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;ds=sidebyside;f=doc%2FREADME.omap3;h=8c3667b10cd18439cbfbc4dcd69f2b5e1da4c2e8;hb=1099b2abef35c3c887f6afac1a8ef18c7924d5d2;hp=0a37de0c7670f7b85c13e91092049226600ad5e9;hpb=c829ff2e3d1bec9b2019480d82638149327db99e;p=oweals%2Fu-boot.git diff --git a/doc/README.omap3 b/doc/README.omap3 index 0a37de0c76..8c3667b10c 100644 --- a/doc/README.omap3 +++ b/doc/README.omap3 @@ -23,13 +23,6 @@ Currently the following boards are supported: * CompuLab Ltd. CM-T35 [8] -Toolchain -========= - -While ARM Cortex-A8 support ARM v7 instruction set (-march=armv7a) we compile -with -march=armv5 to allow more compilers to work. For U-Boot code this has -no performance impact. - Build ===== @@ -48,11 +41,6 @@ make make omap3_evm_config make -* Pandora: - -make omap3_pandora_config -make - * Zoom MDK: make omap3_zoom1_config @@ -68,10 +56,6 @@ make make cm_t35_config make -* BlueLYNX-X: - -make omap3_mvblx_config -make Custom commands =============== @@ -145,6 +129,33 @@ int omap3_dma_wait_for_transfer(uint32_t chan) int omap3_dma_get_revision(uint32_t *minor, uint32_t *major) Read silicon Revision of the DMA module +NAND +==== + +There are some OMAP3 devices out there with NAND attached. Due to the fact that +OMAP3 ROM code can only handle 1-bit hamming ECC for accessing first page +(place where SPL lives) we require this setup for u-boot at least when reading +the second progam within SPL. A lot of newer NAND chips however require more +than 1-bit ECC for the pages, some can live with 1-bit for the first page. To +handle this we can switch to another ECC algorithm after reading the payload +within SPL. + +BCH8 +---- + +To enable hardware assisted BCH8 (8-bit BCH [Bose, Chaudhuri, Hocquenghem]) on +OMAP3 devices we can use the BCH library in lib/bch.c. To do so add CONFIG_BCH +and set CONFIG_NAND_OMAP_ECCSCHEME=5 (refer README.nand) for selecting BCH8_SW. +The NAND OOB layout is the same as in linux kernel, if the linux kernel BCH8 +implementation for OMAP3 works for you so the u-boot version should also. +When you require the SPL to read with BCH8 there are two more configs to +change: + + * CONFIG_SYS_NAND_ECCPOS (must be the same as .eccpos in + GPMC_NAND_HW_BCH8_ECC_LAYOUT defined in + arch/arm/include/asm/arch-omap3/omap_gpmc.h) + * CONFIG_SYS_NAND_ECCSIZE must be 512 + * CONFIG_SYS_NAND_ECCBYTES must be 13 for this BCH8 setup Acknowledgements ================