X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;ds=sidebyside;f=cpu%2Fmpc85xx%2Fstart.S;h=15b804d9fcbfe024139d4b9b2a97d23e7cf821b0;hb=be32bf20bc5bbf3e8cf07085743bbc8f05630812;hp=e8e5eb297de7cf97aacac084b5bcf091b1015e01;hpb=6ea66a818de376ff599c40bdd6c361cfcba2fb6f;p=oweals%2Fu-boot.git

diff --git a/cpu/mpc85xx/start.S b/cpu/mpc85xx/start.S
index e8e5eb297d..15b804d9fc 100644
--- a/cpu/mpc85xx/start.S
+++ b/cpu/mpc85xx/start.S
@@ -757,51 +757,6 @@ in32r:
 	lwbrx	r3,r0,r3
 	blr
 
-/*------------------------------------------------------------------------------- */
-/* Function:	 ppcDcbf */
-/* Description:	 Data Cache block flush */
-/* Input:	 r3 = effective address */
-/* Output:	 none. */
-/*------------------------------------------------------------------------------- */
-	.globl	ppcDcbf
-ppcDcbf:
-	dcbf	r0,r3
-	blr
-
-/*------------------------------------------------------------------------------- */
-/* Function:	 ppcDcbi */
-/* Description:	 Data Cache block Invalidate */
-/* Input:	 r3 = effective address */
-/* Output:	 none. */
-/*------------------------------------------------------------------------------- */
-	.globl	ppcDcbi
-ppcDcbi:
-	dcbi	r0,r3
-	blr
-
-/*--------------------------------------------------------------------------
- * Function:	 ppcDcbz
- * Description:	 Data Cache block zero.
- * Input:	 r3 = effective address
- * Output:	 none.
- *-------------------------------------------------------------------------- */
-
-	.globl	ppcDcbz
-ppcDcbz:
-	dcbz	r0,r3
-	blr
-
-/*------------------------------------------------------------------------------- */
-/* Function:	 ppcSync */
-/* Description:	 Processor Synchronize */
-/* Input:	 none. */
-/* Output:	 none. */
-/*------------------------------------------------------------------------------- */
-	.globl	ppcSync
-ppcSync:
-	sync
-	blr
-
 /*------------------------------------------------------------------------------*/
 
 /*
@@ -1037,7 +992,6 @@ trap_reloc:
 
 	blr
 
-#ifdef CFG_INIT_RAM_LOCK
 .globl unlock_ram_in_cache
 unlock_ram_in_cache:
 	/* invalidate the INIT_RAM section */
@@ -1047,11 +1001,20 @@ unlock_ram_in_cache:
 	andi.	r4,r4,0x1ff
 	slwi	r4,r4,(10 - 1 - L1_CACHE_SHIFT)
 	mtctr	r4
-1:	icbi	r0,r3
-	dcbi	r0,r3
+1:	dcbi	r0,r3
 	addi	r3,r3,CFG_CACHELINE_SIZE
 	bdnz	1b
-	sync			/* Wait for all icbi to complete on bus */
+	sync
+
+	/* Invalidate the TLB entries for the cache */
+	lis	r3,CFG_INIT_RAM_ADDR@h
+	ori	r3,r3,CFG_INIT_RAM_ADDR@l
+	tlbivax	0,r3
+	addi	r3,r3,0x1000
+	tlbivax	0,r3
+	addi	r3,r3,0x1000
+	tlbivax	0,r3
+	addi	r3,r3,0x1000
+	tlbivax	0,r3
 	isync
 	blr
-#endif