X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;ds=sidebyside;f=cpu%2Fmpc5xx%2Fspi.c;h=3ca15ea83860472ebd6d97afc573695f53d69a4a;hb=5891151707ee5902fe62d554c247f42865815757;hp=81c9ddbd4e6147104296c801bec96a07d58b1fd9;hpb=3a473b2a6523db9cdf2b5aed22d9730b4ebc5693;p=oweals%2Fu-boot.git

diff --git a/cpu/mpc5xx/spi.c b/cpu/mpc5xx/spi.c
index 81c9ddbd4e..3ca15ea838 100644
--- a/cpu/mpc5xx/spi.c
+++ b/cpu/mpc5xx/spi.c
@@ -111,7 +111,7 @@ void spi_init_f (void)
 	volatile immap_t *immr;
 	volatile qsmcm5xx_t *qsmcm;
 
-	immr = (immap_t *)  CFG_IMMR;
+	immr = (immap_t *)  CONFIG_SYS_IMMR;
 	qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm;
 
 	qsmcm->qsmcm_qsmcr = 0; /* all accesses enabled */
@@ -128,7 +128,7 @@ void spi_init_f (void)
 	 * PQSPAR[06] = 1 [0x0200] -> PERI: (SPIMOSI)
 	 * PQSPAR[07] = 1 [0x0100] -> PERI: (SPIMISO)
 	 * -------------------------------------------- */
-	qsmcm->qsmcm_pqspar =  0x3 | (CFG_SPI_CS_USED << 3);
+	qsmcm->qsmcm_pqspar =  0x3 | (CONFIG_SYS_SPI_CS_USED << 3);
 
 	 /* --------------------------------------------
 	 * DDRQS[00] = 0 reserved
@@ -160,7 +160,7 @@ void spi_init_f (void)
 	 * PORTQS[14] = 0 [0x0002] -> SPIMOSI Output
 	 * PORTQS[15] = 0 [0x0001] -> SPIMISO Input
 	 * -------------------------------------------- */
-	qsmcm->qsmcm_portqs |= (CFG_SPI_CS_BASE << 3);
+	qsmcm->qsmcm_portqs |= (CONFIG_SYS_SPI_CS_BASE << 3);
 	/* --------------------------------------------
 	 * Controll Register 0
 	 * SPCR0[00] = 1 (0x8000) Master
@@ -208,9 +208,9 @@ void spi_init_f (void)
 	 * Setup RAM
 	 */
 	for(i=0;i<32;i++) {
-	 	 qsmcm->qsmcm_recram[i]=0x0000;
-	 	 qsmcm->qsmcm_tranram[i]=0x0000;
-	 	 qsmcm->qsmcm_comdram[i]=0x00;
+		 qsmcm->qsmcm_recram[i]=0x0000;
+		 qsmcm->qsmcm_tranram[i]=0x0000;
+		 qsmcm->qsmcm_comdram[i]=0x00;
 	}
 	return;
 }
@@ -235,12 +235,12 @@ ssize_t short_spi_write (uchar *addr, int alen, uchar *buffer, int len)
 	volatile immap_t *immr;
 	volatile qsmcm5xx_t *qsmcm;
 
-	immr = (immap_t *)  CFG_IMMR;
+	immr = (immap_t *)  CONFIG_SYS_IMMR;
 	qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm;
 	for(i=0;i<32;i++) {
-	 	 qsmcm->qsmcm_recram[i]=0x0000;
-	 	 qsmcm->qsmcm_tranram[i]=0x0000;
-	 	 qsmcm->qsmcm_comdram[i]=0x00;
+		 qsmcm->qsmcm_recram[i]=0x0000;
+		 qsmcm->qsmcm_tranram[i]=0x0000;
+		 qsmcm->qsmcm_comdram[i]=0x00;
 	}
 	qsmcm->qsmcm_tranram[0] =  SPI_EEPROM_WREN; /* write enable */
 	spi_xfer(1);
@@ -308,13 +308,13 @@ ssize_t short_spi_read (uchar *addr, int alen, uchar *buffer, int len)
 	volatile immap_t *immr;
 	volatile qsmcm5xx_t *qsmcm;
 
-	immr = (immap_t *)  CFG_IMMR;
+	immr = (immap_t *)  CONFIG_SYS_IMMR;
 	qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm;
 
 	for(i=0;i<32;i++) {
-	 	 qsmcm->qsmcm_recram[i]=0x0000;
-	 	 qsmcm->qsmcm_tranram[i]=0x0000;
-	 	 qsmcm->qsmcm_comdram[i]=0x00;
+		 qsmcm->qsmcm_recram[i]=0x0000;
+		 qsmcm->qsmcm_tranram[i]=0x0000;
+		 qsmcm->qsmcm_comdram[i]=0x00;
 	}
 	i=0;
 	qsmcm->qsmcm_tranram[i++] = (SPI_EEPROM_READ); /* READ memory array */
@@ -364,15 +364,15 @@ ssize_t spi_xfer (size_t count)
 	int i;
 	int tm;
 	ushort status;
-	immr = (immap_t *)  CFG_IMMR;
+	immr = (immap_t *)  CONFIG_SYS_IMMR;
 	qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm;
 	DPRINT (("*** spi_xfer entered count %d***\n",count));
 
 	/* Set CS for device */
 	for(i=0;i<(count-1);i++)
-		qsmcm->qsmcm_comdram[i] = 0x80 | CFG_SPI_CS_ACT;  /* CS3 is connected to the SPI EEPROM */
+		qsmcm->qsmcm_comdram[i] = 0x80 | CONFIG_SYS_SPI_CS_ACT;  /* CS3 is connected to the SPI EEPROM */
 
-	qsmcm->qsmcm_comdram[i] = CFG_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */
+	qsmcm->qsmcm_comdram[i] = CONFIG_SYS_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */
 	qsmcm->qsmcm_spcr2=((count-1)&0x1F)<<8;
 
 	DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n", count));