X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;ds=sidebyside;f=cpu%2Farm_cortexa8%2Fcpu.c;h=ca6bf4f23427ded1a70ee6657df96252e2acefd0;hb=792a09eb9d5d8c4f74b7e9f2e887316d511a4e80;hp=ad2085b0103053b4cec233d19cb9afbc01b420b6;hpb=156feb90d200f186cdfd856d7f6f1878bb1bec1e;p=oweals%2Fu-boot.git

diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index ad2085b010..ca6bf4f234 100644
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -6,7 +6,7 @@
  * Marius Groeger <mgroeger@sysgo.de>
  *
  * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <gj@denx.de>
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  *
  * See file CREDITS for list of people who contributed to this
  * project.
@@ -34,6 +34,7 @@
 #include <common.h>
 #include <command.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/system.h>
 
 #ifdef CONFIG_USE_IRQ
 DECLARE_GLOBAL_DATA_PTR;
@@ -45,46 +46,6 @@ void l2cache_disable(void);
 
 static void cache_flush(void);
 
-/* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1(void)
-{
-	unsigned long value;
-
-	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0\
-			     @ read control reg\n":"=r"(value)
-			     ::"memory");
-	return value;
-}
-
-/* write to co-processor 15, register #1 (control register) */
-static void write_p15_c1(unsigned long value)
-{
-	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0\
-			     @ write it back\n"::"r"(value)
-			     : "memory");
-
-	read_p15_c1();
-}
-
-static void cp_delay(void)
-{
-	/* Many OMAP regs need at least 2 nops */
-	asm("nop");
-	asm("nop");
-}
-
-/* See also ARM Ref. Man. */
-#define C1_MMU		(1<<0)	/* mmu off/on */
-#define C1_ALIGN	(1<<1)	/* alignment faults off/on */
-#define C1_DC		(1<<2)	/* dcache off/on */
-#define C1_WB		(1<<3)	/* merging write buffer on/off */
-#define C1_BIG_ENDIAN	(1<<7)	/* big endian off/on */
-#define C1_SYS_PROT	(1<<8)	/* system protection */
-#define C1_ROM_PROT	(1<<9)	/* ROM protection */
-#define C1_IC		(1<<12)	/* icache off/on */
-#define C1_HIGH_VECTORS	(1<<13)	/* location of vectors: low/high addresses */
-#define RESERVED_1	(0xf << 3)	/* must be 111b for R/W */
-
 int cpu_init(void)
 {
 	/*
@@ -134,49 +95,13 @@ int cleanup_before_linux(void)
 	return 0;
 }
 
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-	disable_interrupts();
-	reset_cpu(0);
-
-	/* NOTREACHED */
-	return 0;
-}
-
-void icache_enable(void)
-{
-	ulong reg;
-
-	reg = read_p15_c1();	/* get control reg. */
-	cp_delay();
-	write_p15_c1(reg | C1_IC);
-}
-
-void icache_disable(void)
-{
-	ulong reg;
-
-	reg = read_p15_c1();
-	cp_delay();
-	write_p15_c1(reg & ~C1_IC);
-}
-
-void dcache_disable (void)
-{
-	ulong reg;
-
-	reg = read_p15_c1 ();
-	cp_delay ();
-	write_p15_c1 (reg & ~C1_DC);
-}
-
 void l2cache_enable()
 {
 	unsigned long i;
 	volatile unsigned int j;
 
 	/* ES2 onwards we can disable/enable L2 ourselves */
-	if (get_cpu_rev() == CPU_3430_ES2) {
+	if (get_cpu_rev() >= CPU_3XX_ES20) {
 		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
 		__asm__ __volatile__("orr %0, %0, #0x2":"=r"(i));
 		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
@@ -206,7 +131,7 @@ void l2cache_disable()
 	volatile unsigned int j;
 
 	/* ES2 onwards we can disable/enable L2 ourselves */
-	if (get_cpu_rev() == CPU_3430_ES2) {
+	if (get_cpu_rev() >= CPU_3XX_ES20) {
 		__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i));
 		__asm__ __volatile__("bic %0, %0, #0x2":"=r"(i));
 		__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i));
@@ -229,11 +154,6 @@ void l2cache_disable()
 	}
 }
 
-int icache_status(void)
-{
-	return (read_p15_c1() & C1_IC) != 0;
-}
-
 static void cache_flush(void)
 {
 	asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0));