X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;ds=sidebyside;f=common%2Fcmd_ace.c;h=b6d61057fdebe10e34a80d9746f0ede1a758c565;hb=5498d90312aad9f6bdbf047986027c35b03cd163;hp=4969811f3b28dbe451d4cd3b989f1cb01d3cd917;hpb=08f1080c9cbde2a500e6efe8bc5647a68f183c91;p=oweals%2Fu-boot.git diff --git a/common/cmd_ace.c b/common/cmd_ace.c index 4969811f3b..b6d61057fd 100644 --- a/common/cmd_ace.c +++ b/common/cmd_ace.c @@ -31,6 +31,12 @@ * available to cmd_fat.c:get_dev and filling in a block device * description that has all the bits needed for FAT support to * read sectors. + * + * According to Xilinx technical support, before accessing the + * SystemACE CF you need to set the following control bits: + * FORCECFGMODE : 1 + * CFGMODE : 0 + * CFGSTART : 0 */ # include @@ -50,12 +56,35 @@ */ static unsigned ace_readw(unsigned offset) { - return readw(CFG_SYSTEMACE_BASE+offset); +#if (CFG_SYSTEMACE_WIDTH == 8) + u16 temp; + +#if !defined(__BIG_ENDIAN) + temp =((u16)readb(CFG_SYSTEMACE_BASE+offset) << 8); + temp |= (u16)readb(CFG_SYSTEMACE_BASE+offset+1); +#else + temp = (u16)readb(CFG_SYSTEMACE_BASE+offset); + temp |=((u16)readb(CFG_SYSTEMACE_BASE+offset+1) << 8); +#endif + return temp; +#else + return readw(CFG_SYSTEMACE_BASE+offset); +#endif } static void ace_writew(unsigned val, unsigned offset) { - writew(val, CFG_SYSTEMACE_BASE+offset); +#if (CFG_SYSTEMACE_WIDTH == 8) +#if !defined(__BIG_ENDIAN) + writeb((u8)(val>>8), CFG_SYSTEMACE_BASE+offset); + writeb((u8)val, CFG_SYSTEMACE_BASE+offset+1); +#else + writeb((u8)val, CFG_SYSTEMACE_BASE+offset); + writeb((u8)(val>>8), CFG_SYSTEMACE_BASE+offset+1); +#endif +#else + writew(val, CFG_SYSTEMACE_BASE+offset); +#endif } /* */ @@ -72,7 +101,9 @@ static int get_cf_lock(void) int retry = 10; /* CONTROLREG = LOCKREG */ - ace_writew(0x0002, 0x18); + unsigned val=ace_readw(0x18); + val|=0x0002; + ace_writew((val&0xffff), 0x18); /* Wait for MPULOCK in STATUSREG[15:0] */ while (! (ace_readw(0x04) & 0x0002)) { @@ -89,8 +120,9 @@ static int get_cf_lock(void) static void release_cf_lock(void) { - /* CONTROLREG = none */ - ace_writew(0x0000, 0x18); + unsigned val=ace_readw(0x18); + val&=~(0x0002); + ace_writew((val&0xffff), 0x18); } block_dev_desc_t * systemace_get_dev(int dev) @@ -99,11 +131,15 @@ block_dev_desc_t * systemace_get_dev(int dev) not yet initialized. In that case, fill it in. */ if (systemace_dev.blksz == 0) { systemace_dev.if_type = IF_TYPE_UNKNOWN; + systemace_dev.dev = 0; systemace_dev.part_type = PART_TYPE_UNKNOWN; systemace_dev.type = DEV_TYPE_HARDDISK; systemace_dev.blksz = 512; systemace_dev.removable = 1; systemace_dev.block_read = systemace_read; + + init_part(&systemace_dev); + } return &systemace_dev; @@ -122,6 +158,7 @@ static unsigned long systemace_read(int dev, int retry; unsigned blk_countdown; unsigned char*dp = (unsigned char*)buffer; + unsigned val; if (get_cf_lock() < 0) { unsigned status = ace_readw(0x04); @@ -142,7 +179,7 @@ static unsigned long systemace_read(int dev, retry = 2000; for (;;) { - unsigned val = ace_readw(0x04); + val = ace_readw(0x04); /* If CFDETECT is false, card is missing. */ if (! (val & 0x0010)) { @@ -189,6 +226,11 @@ static unsigned long systemace_read(int dev, /* Write sector count | ReadMemCardData. */ ace_writew((trans&0xff) | 0x0300, 0x14); + /* Reset the configruation controller */ + val = ace_readw(0x18); + val|=0x0080; + ace_writew(val, 0x18); + retry = trans * 16; while (retry > 0) { int idx; @@ -208,6 +250,11 @@ static unsigned long systemace_read(int dev, retry -= 1; } + /* Clear the configruation controller reset */ + val = ace_readw(0x18); + val&=~0x0080; + ace_writew(val, 0x18); + /* Count the blocks we transfer this time. */ start += trans; blk_countdown -= trans;