X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;ds=sidebyside;f=arch%2Farm%2Fmach-socfpga%2Fspl_gen5.c;h=5a7c5ef76d5d097873fa1bc8c7e16e86c099febe;hb=c27178ba3649f539c9f1890ea147f4c5415f63b5;hp=bd2a9fe5aed644ea8290375b9aa4941213a7fb2a;hpb=8b1d3d19be6918ed4488fb1157deabc6c6c42481;p=oweals%2Fu-boot.git

diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c
index bd2a9fe5ae..5a7c5ef76d 100644
--- a/arch/arm/mach-socfpga/spl_gen5.c
+++ b/arch/arm/mach-socfpga/spl_gen5.c
@@ -4,8 +4,10 @@
  */
 
 #include <common.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
 #include <asm/io.h>
-#include <asm/pl310.h>
 #include <asm/u-boot.h>
 #include <asm/utils.h>
 #include <image.h>
@@ -22,17 +24,14 @@
 #include <fdtdec.h>
 #include <watchdog.h>
 #include <dm/uclass.h>
+#include <linux/bitops.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static struct pl310_regs *const pl310 =
-	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
-static const struct socfpga_system_manager *sysmgr_regs =
-	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
-
 u32 spl_boot_device(void)
 {
-	const u32 bsel = readl(&sysmgr_regs->bootinfo);
+	const u32 bsel = readl(socfpga_get_sysmgr_addr() +
+			       SYSMGR_GEN5_BOOTINFO);
 
 	switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
 	case 0x1:	/* FPGA (HPS2FPGA Bridge) */
@@ -53,7 +52,7 @@ u32 spl_boot_device(void)
 }
 
 #ifdef CONFIG_SPL_MMC_SUPPORT
-u32 spl_boot_mode(const u32 boot_device)
+u32 spl_mmc_boot_mode(const u32 boot_device)
 {
 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
 	return MMCSD_MODE_FS;
@@ -63,60 +62,6 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
-static void socfpga_pl310_clear(void)
-{
-	u32 mask = 0xff, ena = 0;
-
-	icache_enable();
-
-	/* Disable the L2 cache */
-	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-
-	writel(0x111, &pl310->pl310_tag_latency_ctrl);
-	writel(0x121, &pl310->pl310_data_latency_ctrl);
-
-	/* enable BRESP, instruction and data prefetch, full line of zeroes */
-	setbits_le32(&pl310->pl310_aux_ctrl,
-		     L310_AUX_CTRL_DATA_PREFETCH_MASK |
-		     L310_AUX_CTRL_INST_PREFETCH_MASK |
-		     L310_SHARED_ATT_OVERRIDE_ENABLE);
-
-	/* Enable the L2 cache */
-	ena = readl(&pl310->pl310_ctrl);
-	ena |= L2X0_CTRL_EN;
-
-	/*
-	 * Invalidate the PL310 L2 cache. Keep the invalidation code
-	 * entirely in L1 I-cache to avoid any bus traffic through
-	 * the L2.
-	 */
-	asm volatile(
-		".align	5			\n"
-		"	b	3f		\n"
-		"1:	str	%1,	[%4]	\n"
-		"	dsb			\n"
-		"	isb			\n"
-		"	str	%0,	[%2]	\n"
-		"	dsb			\n"
-		"	isb			\n"
-		"2:	ldr	%0,	[%2]	\n"
-		"	cmp	%0,	#0	\n"
-		"	bne	2b		\n"
-		"	str	%0,	[%3]	\n"
-		"	dsb			\n"
-		"	isb			\n"
-		"	b	4f		\n"
-		"3:	b	1b		\n"
-		"4:	nop			\n"
-	: "+r"(mask), "+r"(ena)
-	: "r"(&pl310->pl310_inv_way),
-	  "r"(&pl310->pl310_cache_sync), "r"(&pl310->pl310_ctrl)
-	: "memory", "cc");
-
-	/* Disable the L2 cache */
-	clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
-}
-
 void board_init_f(ulong dummy)
 {
 	const struct cm_config *cm_default_cfg = cm_get_default_config();
@@ -124,19 +69,23 @@ void board_init_f(ulong dummy)
 	int ret;
 	struct udevice *dev;
 
+	ret = spl_early_init();
+	if (ret)
+		hang();
+
+	socfpga_get_managers_addr();
+
 	/*
-	 * First C code to run. Clear fake OCRAM ECC first as SBE
+	 * Clear fake OCRAM ECC first as SBE
 	 * and DBE might triggered during power on
 	 */
-	reg = readl(&sysmgr_regs->eccgrp_ocram);
+	reg = readl(socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
 	if (reg & SYSMGR_ECC_OCRAM_SERR)
 		writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
-		       &sysmgr_regs->eccgrp_ocram);
+		       socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
 	if (reg & SYSMGR_ECC_OCRAM_DERR)
 		writel(SYSMGR_ECC_OCRAM_DERR  | SYSMGR_ECC_OCRAM_EN,
-		       &sysmgr_regs->eccgrp_ocram);
-
-	memset(__bss_start, 0, __bss_end - __bss_start);
+		       socfpga_get_sysmgr_addr() + SYSMGR_GEN5_ECCGRP_OCRAM);
 
 	socfpga_sdram_remap_zero();
 	socfpga_pl310_clear();
@@ -175,8 +124,7 @@ void board_init_f(ulong dummy)
 	sysmgr_pinmux_init();
 	sysmgr_config_warmrstcfgio(0);
 
-	/* De-assert reset for peripherals and bridges based on handoff */
-	reset_deassert_peripherals_handoff();
+	/* Set bridges handoff value */
 	socfpga_bridges_set_handoff_regs(true, true, true);
 
 	debug("Unfreezing/Thaw all I/O banks\n");
@@ -188,16 +136,14 @@ void board_init_f(ulong dummy)
 	debug_uart_init();
 #endif
 
-	ret = spl_early_init();
-	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
-
 	ret = uclass_get_device(UCLASS_RESET, 0, &dev);
 	if (ret)
 		debug("Reset init failed: %d\n", ret);
 
+#ifdef CONFIG_SPL_NAND_DENALI
+	clrbits_le32(SOCFPGA_RSTMGR_ADDRESS + RSTMGR_GEN5_PERMODRST, BIT(4));
+#endif
+
 	/* enable console uart printing */
 	preloader_console_init();