X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;ds=sidebyside;f=arch%2Farm%2Fdts%2Ffsl-ls1043a-rdb.dts;h=721b158169db43cf42b23bfea044a173d21621cd;hb=ab1c482440ef33f34d7a4d7a14fe5e99a3704e42;hp=16c5c89d7c799c1c2d94c6e62e058e1151e993e5;hpb=f1993ca066100fcaba7d49fecae0ef604e5807e2;p=oweals%2Fu-boot.git

diff --git a/arch/arm/dts/fsl-ls1043a-rdb.dts b/arch/arm/dts/fsl-ls1043a-rdb.dts
index 16c5c89d7c..721b158169 100644
--- a/arch/arm/dts/fsl-ls1043a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1043a-rdb.dts
@@ -1,13 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
  * Device Tree Include file for Freescale Layerscape-1043A family SoC.
  *
  * Copyright (C) 2015, Freescale Semiconductor
  *
  * Mingkai Hu <Mingkai.hu@freescale.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
  */
 
 /dts-v1/;
@@ -29,7 +26,7 @@
 	dspiflash: n25q12a {
 		#address-cells = <1>;
 		#size-cells = <1>;
-		compatible = "spi-flash";
+		compatible = "jedec,spi-nor";
 		reg = <0>;
 		spi-max-frequency = <1000000>; /* input clock */
 	};
@@ -47,12 +44,12 @@
 		compatible = "adi,adt7461a";
 		reg = <0x4c>;
 	};
-	eeprom@56 {
+	eeprom@52 {
 		compatible = "at24,24c512";
 		reg = <0x52>;
 	};
 
-	eeprom@57 {
+	eeprom@53 {
 		compatible = "at24,24c512";
 		reg = <0x53>;
 	};
@@ -69,8 +66,8 @@
 	#size-cells = <1>;
 	/* NOR, NAND Flashes and FPGA on board */
 	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
-		  0x2 0x0 0x0 0x7e800000 0x00010000
-		  0x3 0x0 0x0 0x7fb00000 0x00000100>;
+		  0x1 0x0 0x0 0x7e800000 0x00010000
+		  0x2 0x0 0x0 0x7fb00000 0x00000100>;
 
 		nor@0,0 {
 			compatible = "cfi-flash";