X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;ds=sidebyside;f=README;h=0d6eac95f37f3a15acda1ad7a10a4b17fb3947ec;hb=45eeb8983c3eca0e82178897c027a34a52295a0f;hp=dc9d97590174ec555fd1fd658c28c7d826c1416c;hpb=11dadd547c08a3480ea153482e99c6ae70b73415;p=oweals%2Fu-boot.git diff --git a/README b/README index dc9d975901..0d6eac95f3 100644 --- a/README +++ b/README @@ -240,57 +240,69 @@ The following options need to be configured: CONFIG_ARM7 CONFIG_PXA250 + MicroBlaze based CPUs: + ---------------------- + CONFIG_MICROBLAZE + - Board Type: Define exactly one of PowerPC based boards: --------------------- - CONFIG_ADCIOP, CONFIG_ICU862 CONFIG_RPXsuper, - CONFIG_ADS860, CONFIG_IP860, CONFIG_SM850, - CONFIG_AMX860, CONFIG_IPHASE4539, CONFIG_SPD823TS, - CONFIG_AR405, CONFIG_IVML24, CONFIG_SXNI855T, - CONFIG_BAB7xx, CONFIG_IVML24_128, CONFIG_Sandpoint8240, - CONFIG_CANBT, CONFIG_IVML24_256, CONFIG_Sandpoint8245, - CONFIG_CCM, CONFIG_IVMS8, CONFIG_TQM823L, - CONFIG_CPCI405, CONFIG_IVMS8_128, CONFIG_TQM850L, - CONFIG_CPCI4052, CONFIG_IVMS8_256, CONFIG_TQM855L, - CONFIG_CPCIISER4, CONFIG_LANTEC, CONFIG_TQM860L, - CONFIG_CPU86, CONFIG_MBX, CONFIG_TQM8260, - CONFIG_CRAYL1, CONFIG_MBX860T, CONFIG_TTTech, - CONFIG_CU824, CONFIG_MHPC, CONFIG_UTX8245, - CONFIG_DASA_SIM, CONFIG_MIP405, CONFIG_W7OLMC, - CONFIG_DU405, CONFIG_MOUSSE, CONFIG_W7OLMG, - CONFIG_ELPPC, CONFIG_MPC8260ADS, CONFIG_WALNUT405, - CONFIG_ERIC, CONFIG_MUSENKI, CONFIG_ZUMA, - CONFIG_ESTEEM192E, CONFIG_MVS1, CONFIG_c2mon, - CONFIG_ETX094, CONFIG_NX823, CONFIG_cogent_mpc8260, - CONFIG_EVB64260, CONFIG_OCRTC, CONFIG_cogent_mpc8xx, - CONFIG_FADS823, CONFIG_ORSG, CONFIG_ep8260, - CONFIG_FADS850SAR, CONFIG_OXC, CONFIG_gw8260, - CONFIG_FADS860T, CONFIG_PCI405, CONFIG_hermes, - CONFIG_FLAGADM, CONFIG_PCIPPC2, CONFIG_hymod, - CONFIG_FPS850L, CONFIG_PCIPPC6, CONFIG_lwmon, - CONFIG_GEN860T, CONFIG_PIP405, CONFIG_pcu_e, - CONFIG_GENIETV, CONFIG_PM826, CONFIG_ppmc8260, - CONFIG_GTH, CONFIG_RPXClassic, CONFIG_rsdproto, - CONFIG_IAD210, CONFIG_RPXlite, CONFIG_sbc8260, - CONFIG_EBONY, CONFIG_sacsng, CONFIG_FPS860L, - CONFIG_V37, CONFIG_ELPT860, CONFIG_CMI, - CONFIG_NETVIA, CONFIG_RBC823, CONFIG_ZPC1900, - CONFIG_MPC8540ADS, CONFIG_MPC8560ADS, CONFIG_QS850, - CONFIG_QS823, CONFIG_QS860T, CONFIG_DB64360, - CONFIG_DB64460, CONFIG_DUET_ADS + CONFIG_ADCIOP CONFIG_GEN860T CONFIG_PCI405 + CONFIG_ADS860 CONFIG_GENIETV CONFIG_PCIPPC2 + CONFIG_AMX860 CONFIG_GTH CONFIG_PCIPPC6 + CONFIG_AR405 CONFIG_gw8260 CONFIG_pcu_e + CONFIG_BAB7xx CONFIG_hermes CONFIG_PIP405 + CONFIG_c2mon CONFIG_hymod CONFIG_PM826 + CONFIG_CANBT CONFIG_IAD210 CONFIG_ppmc8260 + CONFIG_CCM CONFIG_ICU862 CONFIG_QS823 + CONFIG_CMI CONFIG_IP860 CONFIG_QS850 + CONFIG_cogent_mpc8260 CONFIG_IPHASE4539 CONFIG_QS860T + CONFIG_cogent_mpc8xx CONFIG_IVML24 CONFIG_RBC823 + CONFIG_CPCI405 CONFIG_IVML24_128 CONFIG_RPXClassic + CONFIG_CPCI4052 CONFIG_IVML24_256 CONFIG_RPXlite + CONFIG_CPCIISER4 CONFIG_IVMS8 CONFIG_RPXsuper + CONFIG_CPU86 CONFIG_IVMS8_128 CONFIG_rsdproto + CONFIG_CRAYL1 CONFIG_IVMS8_256 CONFIG_sacsng + CONFIG_CSB272 CONFIG_JSE CONFIG_Sandpoint8240 + CONFIG_CU824 CONFIG_LANTEC CONFIG_Sandpoint8245 + CONFIG_DASA_SIM CONFIG_lwmon CONFIG_sbc8260 + CONFIG_DB64360 CONFIG_MBX CONFIG_sbc8560 + CONFIG_DB64460 CONFIG_MBX860T CONFIG_SM850 + CONFIG_DU405 CONFIG_MHPC CONFIG_SPD823TS + CONFIG_DUET_ADS CONFIG_MIP405 CONFIG_STXGP3 + CONFIG_EBONY CONFIG_MOUSSE CONFIG_SXNI855T + CONFIG_ELPPC CONFIG_MPC8260ADS CONFIG_TQM823L + CONFIG_ELPT860 CONFIG_MPC8540ADS CONFIG_TQM8260 + CONFIG_ep8260 CONFIG_MPC8560ADS CONFIG_TQM850L + CONFIG_ERIC CONFIG_MUSENKI CONFIG_TQM855L + CONFIG_ESTEEM192E CONFIG_MVS1 CONFIG_TQM860L + CONFIG_ETX094 CONFIG_NETPHONE CONFIG_TTTech + CONFIG_EVB64260 CONFIG_NETTA CONFIG_UTX8245 + CONFIG_FADS823 CONFIG_NETVIA CONFIG_V37 + CONFIG_FADS850SAR CONFIG_NX823 CONFIG_W7OLMC + CONFIG_FADS860T CONFIG_OCRTC CONFIG_W7OLMG + CONFIG_FLAGADM CONFIG_ORSG CONFIG_WALNUT405 + CONFIG_FPS850L CONFIG_OXC CONFIG_ZPC1900 + CONFIG_FPS860L CONFIG_ZUMA ARM based boards: ----------------- - CONFIG_HHP_CRADLE, CONFIG_DNP1110, CONFIG_EP7312, - CONFIG_IMPA7, CONFIG_LART, CONFIG_LUBBOCK, - CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610, - CONFIG_H2_OMAP1610, CONFIG_SHANNON, CONFIG_SMDK2400, - CONFIG_SMDK2410, CONFIG_TRAB, CONFIG_VCMA9, - CONFIG_AT91RM9200DK + CONFIG_AT91RM9200DK, CONFIG_CERF250, CONFIG_DNP1110, + CONFIG_EP7312, CONFIG_H2_OMAP1610, CONFIG_HHP_CRADLE, + CONFIG_IMPA7, CONFIG_INNOVATOROMAP1510, CONFIG_INNOVATOROMAP1610, + CONFIG_LART, CONFIG_LPD7A400 CONFIG_LUBBOCK, + CONFIG_OSK_OMAP5912, CONFIG_SHANNON, CONFIG_P2_OMAP730, + CONFIG_SMDK2400, CONFIG_SMDK2410, CONFIG_TRAB, + CONFIG_VCMA9 + + MicroBlaze based boards: + ------------------------ + + CONFIG_SUZAKU - CPU Module Type: (if CONFIG_COGENT is defined) @@ -320,7 +332,7 @@ The following options need to be configured: CFG_8260ADS - original MPC8260ADS CFG_8266ADS - MPC8266ADS CFG_PQ2FADS - PQ2FADS-ZU or PQ2FADS-VR - + CFG_8272ADS - MPC8272ADS - MPC824X Family Member (if CONFIG_MPC824X is defined) Define exactly one of @@ -441,8 +453,8 @@ The following options need to be configured: (RTS/CTS) and UART's built-in FIFO. Set the number of bytes the interrupt driven input buffer should have. - Set to 0 to disable this feature (this is the default). - This will also disable hardware handshake. + Leave undefined to disable this feature, including + disable the buffer and hardware handshake. - Console UART Number: CONFIG_UART1_CONSOLE @@ -561,7 +573,7 @@ The following options need to be configured: CFG_CMD_LOADB loadb CFG_CMD_LOADS loads CFG_CMD_MEMORY md, mm, nm, mw, cp, cmp, crc, base, - loop, mtest + loop, loopw, mtest CFG_CMD_MISC Misc functions like sleep etc CFG_CMD_MMC MMC memory mapped support CFG_CMD_MII MII utility commands @@ -581,16 +593,17 @@ The following options need to be configured: CFG_CMD_USB * USB support CFG_CMD_VFD * VFD support (TRAB) CFG_CMD_BSP * Board SPecific functions + CFG_CMD_CDP * Cisco Discover Protocol support ----------------------------------------------- CFG_CMD_ALL all - CFG_CMD_DFL Default configuration; at the moment + CONFIG_CMD_DFL Default configuration; at the moment this is includes all commands, except the ones marked with "*" in the list above. If you don't define CONFIG_COMMANDS it defaults to - CFG_CMD_DFL in include/cmd_confdefs.h. A board can + CONFIG_CMD_DFL in include/cmd_confdefs.h. A board can override the default settings in the respective include file. @@ -640,6 +653,7 @@ The following options need to be configured: CONFIG_RTC_DS1337 - use Maxim, Inc. DS1337 RTC CONFIG_RTC_DS1338 - use Maxim, Inc. DS1338 RTC CONFIG_RTC_DS164x - use Dallas DS164x RTC + CONFIG_RTC_MAX6900 - use Maxim, Inc. MAX6900 RTC Note that if the RTC uses I2C, then the I2C interface must also be configured. See I2C Support, below. @@ -660,16 +674,31 @@ The following options need to be configured: one partition type as well. - IDE Reset method: - CONFIG_IDE_RESET_ROUTINE + CONFIG_IDE_RESET_ROUTINE - this is defined in several + board configurations files but used nowhere! - Set this to define that instead of a reset Pin, the - routine ide_set_reset(int idereset) will be used. + CONFIG_IDE_RESET - is this is defined, IDE Reset will + be performed by calling the function + ide_set_reset(int reset) + which has to be defined in a board specific file - ATAPI Support: CONFIG_ATAPI Set this to enable ATAPI support. +- LBA48 Support + CONFIG_LBA48 + + Set this to enable support for disks larger than 137GB + Also look at CFG_64BIT_LBA ,CFG_64BIT_VSPRINTF and CFG_64BIT_STRTOUL + Whithout these , LBA48 support uses 32bit variables and will 'only' + support disks up to 2.1TB. + + CFG_64BIT_LBA: + When enabled, makes the IDE subsystem use 64bit sector addresses. + Default is 32bit. + - SCSI Support: At the moment only there is only support for the SYM53C8XX SCSI controller; define @@ -714,9 +743,23 @@ The following options need to be configured: CONFIG_LAN91C96_USE_32_BIT Define this to enable 32 bit addressing + CONFIG_DRIVER_SMC91111 + Support for SMSC's LAN91C111 chip + + CONFIG_SMC91111_BASE + Define this to hold the physical address + of the device (I/O space) + + CONFIG_SMC_USE_32_BIT + Define this if data bus is 32 bits + + CONFIG_SMC_USE_IOFUNCS + Define this to use i/o functions instead of macros + (some hardware wont work with macros) + - USB Support: At the moment only the UHCI host controller is - supported (PIP405, MIP405); define + supported (PIP405, MIP405, MPC5200); define CONFIG_USB_UHCI to enable it. define CONFIG_USB_KEYBOARD to enable the USB Keyboard end define CONFIG_USB_STORAGE to enable the USB @@ -724,6 +767,13 @@ The following options need to be configured: Note: Supported are USB Keyboards and USB Floppy drives (TEAC FD-05PUB). + MPC5200 USB requires additional defines: + CONFIG_USB_CLOCK + for 528 MHz Clock: 0x0001bbbb + CONFIG_USB_CONFIG + for differential drivers: 0x00001000 + for single ended drivers: 0x00005000 + - MMC Support: The MMC controller on the Intel PXA is supported. To @@ -756,17 +806,30 @@ The following options need to be configured: Enable Chips & Technologies 69000 Video chip CONFIG_VIDEO_SMI_LYNXEM - Enable Silicon Motion SMI 712/710/810 Video chip - Videomode are selected via environment 'videomode' with - standard LiLo mode numbers. - Following modes are supported (* is default): - - 800x600 1024x768 1280x1024 - 256 (8bit) 303* 305 307 - 65536 (16bit) 314 317 31a - 16,7 Mill (24bit) 315 318 31b + Enable Silicon Motion SMI 712/710/810 Video chip. The + video output is selected via environment 'videoout' + (1 = LCD and 2 = CRT). If videoout is undefined, CRT is + assumed. + + For the CT69000 and SMI_LYNXEM drivers, videomode is + selected via environment 'videomode'. Two diferent ways + are possible: + - "videomode=num" 'num' is a standard LiLo mode numbers. + Following standard modes are supported (* is default): + + Colors 640x480 800x600 1024x768 1152x864 1280x1024 + -------------+--------------------------------------------- + 8 bits | 0x301* 0x303 0x305 0x161 0x307 + 15 bits | 0x310 0x313 0x316 0x162 0x319 + 16 bits | 0x311 0x314 0x317 0x163 0x31A + 24 bits | 0x312 0x315 0x318 ? 0x31B + -------------+--------------------------------------------- (i.e. setenv videomode 317; saveenv; reset;) + - "videomode=bootargs" all the video parameters are parsed + from the bootargs. (See drivers/videomodes.c) + + CONFIG_VIDEO_SED13806 Enable Epson SED13806 driver. This driver supports 8bpp and 16bpp modes defined by CONFIG_VIDEO_SED13806_8BPP @@ -833,7 +896,7 @@ The following options need to be configured: If this option is set, the environment is checked for a variable "splashimage". If found, the usual display of logo, copyright and system information on the LCD - is supressed and the BMP image at the address + is suppressed and the BMP image at the address specified in "splashimage" is loaded instead. The console is redirected to the "nulldev", too. This allows for a "silent" boot where a splash screen is @@ -850,6 +913,32 @@ The following options need to be configured: the malloc area (as defined by CFG_MALLOC_LEN) should be at least 4MB. +- MII/PHY support: + CONFIG_PHY_ADDR + + The address of PHY on MII bus. + + CONFIG_PHY_CLOCK_FREQ (ppc4xx) + + The clock frequency of the MII bus + + CONFIG_PHY_GIGE + + If this option is set, support for speed/duplex + detection of Gigabit PHY is included. + + CONFIG_PHY_RESET_DELAY + + Some PHY like Intel LXT971A need extra delay after + reset before any MII register access is possible. + For such PHY, set this option to the usec delay + required. (minimum 300usec for LXT971A) + + CONFIG_PHY_CMD_DELAY (ppc4xx) + + Some PHY like Intel LXT971A need extra delay after + command issued before MII status register can be read + - Ethernet address: CONFIG_ETHADDR CONFIG_ETH2ADDR @@ -914,6 +1003,48 @@ The following options need to be configured: environment variable is passed as option 12 to the DHCP server. + - CDP Options: + CONFIG_CDP_DEVICE_ID + + The device id used in CDP trigger frames. + + CONFIG_CDP_DEVICE_ID_PREFIX + + A two character string which is prefixed to the MAC address + of the device. + + CONFIG_CDP_PORT_ID + + A printf format string which contains the ascii name of + the port. Normally is set to "eth%d" which sets + eth0 for the first ethernet, eth1 for the second etc. + + CONFIG_CDP_CAPABILITIES + + A 32bit integer which indicates the device capabilities; + 0x00000010 for a normal host which does not forwards. + + CONFIG_CDP_VERSION + + An ascii string containing the version of the software. + + CONFIG_CDP_PLATFORM + + An ascii string containing the name of the platform. + + CONFIG_CDP_TRIGGER + + A 32bit integer sent on the trigger. + + CONFIG_CDP_POWER_CONSUMPTION + + A 16bit integer containing the power consumption of the + device in .1 of milliwatts. + + CONFIG_CDP_APPLIANCE_VLAN_TYPE + + A byte containing the id of the VLAN. + - Status LED: CONFIG_STATUS_LED Several configurations allow to display the current @@ -1042,6 +1173,12 @@ The following options need to be configured: custom i2c_init_board() routine in boards/xxx/board.c is run early in the boot sequence. + CONFIG_I2CFAST (PPC405GP|PPC405EP only) + + This option enables configuration of bi_iic_fast[] flags + in u-boot bd_info structure based on u-boot environment + variable "i2cfast". (see also i2cfast) + - SPI Support: CONFIG_SPI Enables SPI driver (so far only tested with @@ -1196,6 +1333,10 @@ The following options need to be configured: default value of 5 is used. - Command Interpreter: + CFG_AUTO_COMPLETE + + Enable auto completion of commands using TAB. + CFG_HUSH_PARSER Define this variable to enable the "hush" shell (from @@ -1660,6 +1801,17 @@ to save the current settings. The length in bytes of the EEPROM memory array address. Note that this is NOT the chip address length! + - CFG_I2C_EEPROM_ADDR_OVERFLOW: + EEPROM chips that implement "address overflow" are ones + like Catalyst 24WC04/08/16 which has 9/10/11 bits of + address and the extra bits end up in the "chip address" bit + slots. This makes a 24WC08 (1Kbyte) chip look like four 256 + byte chips. + + Note that we consider the length of the address field to + still be one byte because the extra address bits are hidden + in the chip address. + - CFG_EEPROM_SIZE: The size in bytes of the EEPROM device. @@ -1677,6 +1829,16 @@ to save the current settings. environment area within the total memory of your DataFlash placed at the specified address. +- CFG_ENV_IS_IN_NAND: + + Define this if you have a NAND device which you want to use + for the environment. + + - CFG_ENV_OFFSET: + - CFG_ENV_SIZE: + + These two #defines specify the offset and size of the environment + area within the first NAND device. - CFG_SPI_INIT_OFFSET @@ -1713,6 +1875,13 @@ use the "saveenv" command to store a valid environment. - CFG_FAULT_MII_ADDR: MII address of the PHY to check for the Ethernet link state. +- CFG_64BIT_VSPRINTF: + Makes vsprintf (and all *printf functions) support printing + of 64bit values by using the L quantifier + +- CFG_64BIT_STRTOUL: + Adds simple_strtoull that returns a 64bit value + Low Level (hardware related) configuration options: --------------------------------------------------- @@ -1854,6 +2023,40 @@ Low Level (hardware related) configuration options: CFG_POCMR2_MASK_ATTRIB: (MPC826x only) Overrides the default PCI memory map in cpu/mpc8260/pci.c if set. +- CONFIG_ETHER_ON_FEC[12] + Define to enable FEC[12] on a 8xx series processor. + +- CONFIG_FEC[12]_PHY + Define to the hardcoded PHY address which corresponds + to the given FEC; i. e. + #define CONFIG_FEC1_PHY 4 + means that the PHY with address 4 is connected to FEC1 + + When set to -1, means to probe for first available. + +- CONFIG_FEC[12]_PHY_NORXERR + The PHY does not have a RXERR line (RMII only). + (so program the FEC to ignore it). + +- CONFIG_RMII + Enable RMII mode for all FECs. + Note that this is a global option, we can't + have one FEC in standard MII mode and another in RMII mode. + +- CONFIG_CRC32_VERIFY + Add a verify option to the crc32 command. + The syntax is: + + => crc32 -v