X-Git-Url: https://git.librecmc.org/?a=blobdiff_plain;ds=inline;f=drivers%2Fserial%2Fserial_pl01x.c;h=552c945264c8d549c6da6fbbb311beb188fcb66c;hb=b81406db51a68ddd482d4ea3641dd7ad2e910771;hp=ecf3bc02409e4a741353cd97404f827ea18e7896;hpb=850f788709cef8f7d53d571aec3bfb73b14c5531;p=oweals%2Fu-boot.git diff --git a/drivers/serial/serial_pl01x.c b/drivers/serial/serial_pl01x.c index ecf3bc0240..552c945264 100644 --- a/drivers/serial/serial_pl01x.c +++ b/drivers/serial/serial_pl01x.c @@ -80,13 +80,6 @@ static int pl01x_generic_serial_init(struct pl01x_regs *regs, writel(0, ®s->pl010_cr); break; case TYPE_PL011: -#ifdef CONFIG_PL011_SERIAL_FLUSH_ON_INIT - /* Empty RX fifo if necessary */ - if (readl(®s->pl011_cr) & UART_PL011_CR_UARTEN) { - while (!(readl(®s->fr) & UART_PL01x_FR_RXFE)) - readl(®s->dr); - } -#endif /* disable everything */ writel(0, ®s->pl011_cr); break; @@ -105,21 +98,6 @@ static int pl011_set_line_control(struct pl01x_regs *regs) * control register write */ lcr = UART_PL011_LCRH_WLEN_8 | UART_PL011_LCRH_FEN; -#ifdef CONFIG_PL011_SERIAL_RLCR - { - int i; - - /* - * Program receive line control register after waiting - * 10 bus cycles. Delay be writing to readonly register - * 10 times - */ - for (i = 0; i < 10; i++) - writel(lcr, ®s->fr); - - writel(lcr, ®s->pl011_rlcr); - } -#endif writel(lcr, ®s->pl011_lcrh); return 0; } @@ -389,3 +367,31 @@ U_BOOT_DRIVER(serial_pl01x) = { }; #endif + +#if defined(CONFIG_DEBUG_UART_PL010) || defined(CONFIG_DEBUG_UART_PL011) + +#include + +static void _debug_uart_init(void) +{ +#ifndef CONFIG_DEBUG_UART_SKIP_INIT + struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE; + enum pl01x_type type = CONFIG_IS_ENABLED(DEBUG_UART_PL011) ? + TYPE_PL011 : TYPE_PL010; + + pl01x_generic_serial_init(regs, type); + pl01x_generic_setbrg(regs, type, + CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE); +#endif +} + +static inline void _debug_uart_putc(int ch) +{ + struct pl01x_regs *regs = (struct pl01x_regs *)CONFIG_DEBUG_UART_BASE; + + pl01x_putc(regs, ch); +} + +DEBUG_UART_FUNCS + +#endif