PLL/clocks settings in FLASH and O/C recovery for AR9331, other minor changes, AR9344...

[oweals/u-boot_mod.git] / u-boot / lib_mips / time.c

diff --git a/u-boot/lib_mips/time.c b/u-boot/lib_mips/time.c
index 03ed468f913708605aa27bf65f1c06c8dcae00e1..709d385cb6bd25904b663ba64c831aec6b3401d3 100755 (executable)
--- a/u-boot/lib_mips/time.c
+++ b/u-boot/lib_mips/time.c
@@ -23,6 +23,8 @@
 
 #include <common.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static inline void mips_compare_set(u32 v){
        asm volatile ("mtc0 %0, $11" : : "r" (v));
 }
@@ -35,7 +37,7 @@ static inline u32 mips_count_get(void){
        u32 count;
 
        asm volatile ("mfc0 %0, $9" : "=r" (count) :);
-       return count;
+       return(count);
 }
 
 /*
@@ -45,18 +47,28 @@ int timer_init(void){
        mips_compare_set(0);
        mips_count_set(0);
 
-       return 0;
+       return(0);
 }
 
 ulong get_timer(ulong base){
-       return mips_count_get() - base;
+       return(mips_count_get() - base);
 }
 
 void udelay(unsigned long usec){
        ulong tmo;
        ulong start = get_timer(0);
+       bd_t *bd = gd->bd;
+
+       /*
+        * We don't have filled the bd->bi_cfg_hz
+        * before relocation to RAM (bd is read only before that),
+        */
+       if((gd->flags & GD_FLG_RELOC) == 0){
+               tmo = usec * (CFG_HZ_FALLBACK / 1000000);
+       } else {
+               tmo = usec * (CFG_HZ / 1000000);
+       }
 
-       tmo = usec * (CFG_HZ / 1000000);
        while ((ulong)((mips_count_get() - start)) < tmo)
                /*NOP*/;
 }