#define CONFIG_QCA_GPIO_MASK_IN GPIO17
#define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
+#elif defined(CONFIG_FOR_P2W_CPE505N)
+
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO4 | GPIO11 | GPIO12 |\
+ GPIO14 | GPIO15
+ #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_IN GPIO17
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
+#elif defined(CONFIG_FOR_P2W_R602N)
+
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO4 | GPIO11 | GPIO12 |\
+ GPIO14 | GPIO15 | GPIO16
+ #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_IN GPIO17
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
+#elif defined(CONFIG_FOR_TPLINK_WA850RE_V2)
+
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO0 | GPIO1 | GPIO2 |\
+ GPIO3 | GPIO4 | GPIO12 |\
+ GPIO13 | GPIO14
+ #define CONFIG_QCA_GPIO_MASK_OUT GPIO15 |\
+ CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_IN GPIO16 | GPIO17
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO15 |\
+ CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
+#elif defined(CONFIG_FOR_TPLINK_WR810N)
+
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO13
+ #define CONFIG_QCA_GPIO_MASK_OUT GPIO11 |\
+ CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_IN GPIO0 | GPIO1 | GPIO12
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO11 |\
+ CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
#elif defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
defined(CONFIG_FOR_TPLINK_WR802N)
#define CONFIG_QCA_GPIO_MASK_IN GPIO12 | GPIO17
#define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
+#elif defined(CONFIG_FOR_TPLINK_WR842N_V3)
+
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO2 | GPIO3 | GPIO4 |\
+ GPIO11 | GPIO12 | GPIO13 |\
+ GPIO14 | GPIO15 | GPIO16 |\
+ GPIO17
+ #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_IN GPIO0 | GPIO1
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
+#elif defined(CONFIG_FOR_TPLINK_WR902AC_V1)
+
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO4 | GPIO13 | GPIO15
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO0 | GPIO11 | GPIO12
+ #define CONFIG_QCA_GPIO_MASK_OUT GPIO1 |\
+ CONFIG_QCA_GPIO_MASK_LED_ACT_H |\
+ CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_IN GPIO2 | GPIO3 | GPIO14 | GPIO17
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO1 |\
+ CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
+
#elif defined(CONFIG_FOR_WALLYS_DR531)
#define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO11 | GPIO12 | GPIO13 |\
"rootfstype=jffs2 init=/sbin/init "\
"mtdparts=ath-nor0:64k(u-boot),64k(art),1536k(uImage),6464k(rootfs),64k(mib0)"
+#elif defined(CONFIG_FOR_P2W_CPE505N) ||\
+ defined(CONFIG_FOR_P2W_R602N) ||\
+ defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
+ defined(CONFIG_FOR_YUNCORE_CPE830) ||\
+ defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
+
+ #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
+ "rootfstype=squashfs init=/sbin/init "\
+ "mtdparts=spi0.0:256k(u-boot),64k(u-boot-env),14528k(rootfs),1472k(kernel),64k(art),16000k(firmware)"
+
+#elif defined(CONFIG_FOR_TPLINK_WR810N)
+
+ #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
+ "rootfstype=squashfs init=/sbin/init "\
+ "mtdparts=ath-nor0:128k(u-boot),1024k(kernel),6912k(rootfs),64k(config),64k(art)"
+
#elif defined(CONFIG_FOR_TPLINK_WR820N_CN)
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
"rootfstype=squashfs init=/sbin/init "\
"mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(art)"
-#elif defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
+#elif defined(CONFIG_FOR_TPLINK_WA850RE_V2) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
defined(CONFIG_FOR_TPLINK_WR841N_V11) ||\
defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\
defined(CONFIG_FOR_TPLINK_WR802N)
"rootfstype=squashfs init=/sbin/init "\
"mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
-#elif defined(CONFIG_FOR_WALLYS_DR531)
+#elif defined(CONFIG_FOR_TPLINK_WR842N_V3) ||\
+ defined(CONFIG_FOR_TPLINK_WR902AC_V1)
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
"rootfstype=jffs2 init=/sbin/init "\
- "mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k"
+ "mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(ART)"
-#elif defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
- defined(CONFIG_FOR_YUNCORE_CPE830) ||\
- defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
+#elif defined(CONFIG_FOR_WALLYS_DR531)
#define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
- "rootfstype=squashfs init=/sbin/init "\
- "mtdparts=spi0.0:256k(u-boot),64k(u-boot-env),14528k(rootfs),1472k(kernel),64k(art),16000k(firmware)"
+ "rootfstype=jffs2 init=/sbin/init "\
+ "mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),64k(mib0),64k(ART)"
#endif
defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
defined(CONFIG_FOR_COMFAST_CF_E530N) ||\
+ defined(CONFIG_FOR_TPLINK_WA850RE_V2) ||\
defined(CONFIG_FOR_TPLINK_WR802N) ||\
+ defined(CONFIG_FOR_TPLINK_WR810N) ||\
defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
defined(CONFIG_FOR_TPLINK_WR841N_V11) ||\
- defined(CONFIG_FOR_TPLINK_WR841N_V9)
+ defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\
+ defined(CONFIG_FOR_TPLINK_WR842N_V3) ||\
+ defined(CONFIG_FOR_TPLINK_WR902AC_V1)
#define CFG_LOAD_ADDR 0x9F020000
-#elif defined(CONFIG_FOR_WALLYS_DR531)
- #define CFG_LOAD_ADDR 0x9F050000
-#elif defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
+#elif defined(CONFIG_FOR_P2W_CPE505N) ||\
+ defined(CONFIG_FOR_P2W_R602N) ||\
+ defined(CONFIG_FOR_WALLYS_DR531) ||\
+ defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
defined(CONFIG_FOR_YUNCORE_CPE830) ||\
defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
- #define CFG_LOAD_ADDR 0x9FE80000
+ #define CFG_LOAD_ADDR 0x9F050000
#endif
-#define CONFIG_BOOTCOMMAND "bootm " MK_STR(CFG_LOAD_ADDR)
+#if defined(CONFIG_FOR_P2W_CPE505N) ||\
+ defined(CONFIG_FOR_P2W_R602N) ||\
+ defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
+ defined(CONFIG_FOR_YUNCORE_CPE830) ||\
+ defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
+ #define CONFIG_BOOTCOMMAND "bootm 0x9F050000 || bootm 0x9FE80000"
+#else
+ #define CONFIG_BOOTCOMMAND "bootm " MK_STR(CFG_LOAD_ADDR)
+#endif
/*
* =========================
#define CFG_ENV_ADDR 0x9F018000
#define CFG_ENV_SIZE 0x7C00
#define CFG_ENV_SECT_SIZE 0x10000
-#elif defined(CONFIG_FOR_TPLINK_WR802N) ||\
+#elif defined(CONFIG_FOR_P2W_CPE505N) ||\
+ defined(CONFIG_FOR_P2W_R602N) ||\
+ defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
+ defined(CONFIG_FOR_YUNCORE_CPE830) ||\
+ defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
+ #define CFG_ENV_ADDR 0x9F040000
+ #define CFG_ENV_SIZE 0xFC00
+ #define CFG_ENV_SECT_SIZE 0x10000
+#elif defined(CONFIG_FOR_TPLINK_WA850RE_V2) ||\
+ defined(CONFIG_FOR_TPLINK_WR802N) ||\
+ defined(CONFIG_FOR_TPLINK_WR810N) ||\
defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
defined(CONFIG_FOR_TPLINK_WR841N_V11) ||\
- defined(CONFIG_FOR_TPLINK_WR841N_V9)
+ defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\
+ defined(CONFIG_FOR_TPLINK_WR842N_V3) ||\
+ defined(CONFIG_FOR_TPLINK_WR902AC_V1)
#define CFG_ENV_ADDR 0x9F01EC00
#define CFG_ENV_SIZE 0x1000
#define CFG_ENV_SECT_SIZE 0x10000
#define CFG_ENV_ADDR 0x9F030000
#define CFG_ENV_SIZE 0xF800
#define CFG_ENV_SECT_SIZE 0x10000
-#elif defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
- defined(CONFIG_FOR_YUNCORE_CPE830) ||\
- defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
- #define CFG_ENV_ADDR 0x9F040000
- #define CFG_ENV_SIZE 0xFC00
- #define CFG_ENV_SECT_SIZE 0x10000
#endif
/*
#define OFFSET_MAC_DATA_BLOCK 0x10000
#define OFFSET_MAC_DATA_BLOCK_LENGTH 0x10000
#define OFFSET_MAC_ADDRESS 0x00000
+#elif defined(CONFIG_FOR_P2W_CPE505N) ||\
+ defined(CONFIG_FOR_P2W_R602N) ||\
+ defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
+ defined(CONFIG_FOR_YUNCORE_CPE830) ||\
+ defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
+ #define OFFSET_MAC_DATA_BLOCK 0xFF0000
+ #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
+ #define OFFSET_MAC_ADDRESS 0x000000
+#elif defined(CONFIG_FOR_TPLINK_WA850RE_V2)
+ #define OFFSET_MAC_DATA_BLOCK 0x3c0000
+ #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
+ #define OFFSET_MAC_ADDRESS 0x000008
#elif defined(CONFIG_FOR_TPLINK_WR802N) ||\
+ defined(CONFIG_FOR_TPLINK_WR810N) ||\
defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
defined(CONFIG_FOR_TPLINK_WR841N_V11) ||\
- defined(CONFIG_FOR_TPLINK_WR841N_V9)
+ defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\
+ defined(CONFIG_FOR_TPLINK_WR842N_V3)
#define OFFSET_MAC_DATA_BLOCK 0x010000
#define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
#define OFFSET_MAC_ADDRESS 0x00FC00
#define OFFSET_ROUTER_MODEL 0x00FD00
#define OFFSET_PIN_NUMBER 0x00FE00
+#elif defined(CONFIG_FOR_TPLINK_WR902AC_V1)
+ #define OFFSET_MAC_DATA_BLOCK 0x750000
+ #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
+ #define OFFSET_MAC_ADDRESS 0x000008
#elif defined(CONFIG_FOR_WALLYS_DR531)
#define OFFSET_MAC_DATA_BLOCK 0x030000
#define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
#define OFFSET_MAC_ADDRESS 0x00F810
-#elif defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
- defined(CONFIG_FOR_YUNCORE_CPE830) ||\
- defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
- #define OFFSET_MAC_DATA_BLOCK 0xFF0000
- #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
- #define OFFSET_MAC_ADDRESS 0x000000
#endif
/*
#undef CONFIG_CMD_DHCP
#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_SNTP
+ #undef CONFIG_UPG_SCRIPTS_UBOOT
#endif
/*
* HTTP recovery configuration
* ===========================
*/
-#if defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
- defined(CONFIG_FOR_YUNCORE_CPE830) ||\
- defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
- #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS CFG_FLASH_BASE + 0x50000
-#else
- #define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS CFG_LOAD_ADDR
+#define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS CFG_LOAD_ADDR
+
+#if defined(CONFIG_FOR_COMFAST_CF_E314N) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E530N)
+ #define WEBFAILSAFE_UPLOAD_ART_ADDRESS (CFG_FLASH_BASE + 0x10000)
#endif
/* Firmware size limit */
defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
defined(CONFIG_FOR_COMFAST_CF_E530N) ||\
defined(CONFIG_FOR_TPLINK_WR802N) ||\
+ defined(CONFIG_FOR_TPLINK_WR810N) ||\
defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
defined(CONFIG_FOR_TPLINK_WR841N_V11) ||\
- defined(CONFIG_FOR_TPLINK_WR841N_V9)
+ defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\
+ defined(CONFIG_FOR_TPLINK_WR842N_V3)
#define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024)
-#elif defined(CONFIG_FOR_WALLYS_DR531) ||\
+#elif defined(CONFIG_FOR_TPLINK_WA850RE_V2)
+ #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (448 * 1024)
+#elif defined(CONFIG_FOR_TPLINK_WR902AC_V1)
+ #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (832 * 1024)
+#elif defined(CONFIG_FOR_P2W_CPE505N) ||\
+ defined(CONFIG_FOR_P2W_R602N) ||\
+ defined(CONFIG_FOR_WALLYS_DR531) ||\
defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
defined(CONFIG_FOR_YUNCORE_CPE830) ||\
defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
* PLL/Clocks configuration
* ========================
*/
-#if defined(CONFIG_FOR_TPLINK_WR802N) ||\
- defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
+#if defined(CONFIG_FOR_TPLINK_WA850RE_V2) ||\
+ defined(CONFIG_FOR_TPLINK_WR802N) ||\
+ defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
defined(CONFIG_FOR_TPLINK_WR841N_V9)
#define CONFIG_QCA_PLL QCA_PLL_PRESET_550_400_200
#else
defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
defined(CONFIG_FOR_COMFAST_CF_E530N) ||\
+ defined(CONFIG_FOR_TPLINK_WA850RE_V2) ||\
defined(CONFIG_FOR_TPLINK_WR802N) ||\
+ defined(CONFIG_FOR_TPLINK_WR810N) ||\
defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
defined(CONFIG_FOR_TPLINK_WR841N_V11) ||\
- defined(CONFIG_FOR_TPLINK_WR841N_V9)
+ defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\
+ defined(CONFIG_FOR_TPLINK_WR842N_V3) ||\
+ defined(CONFIG_FOR_TPLINK_WR902AC_V1)
#define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x10000
#define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000
-#elif defined(CONFIG_FOR_WALLYS_DR531)
-
- #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x30000
- #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000
-
-#elif defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
+#elif defined(CONFIG_FOR_P2W_CPE505N) ||\
+ defined(CONFIG_FOR_P2W_R602N) ||\
+ defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
defined(CONFIG_FOR_YUNCORE_CPE830) ||\
defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
#define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x40000
#define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000
+#elif defined(CONFIG_FOR_WALLYS_DR531)
+
+ #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x30000
+ #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000
+
#endif
/*
!defined(CONFIG_FOR_COMFAST_CF_E320N_V2) &&\
!defined(CONFIG_FOR_COMFAST_CF_E520N) &&\
!defined(CONFIG_FOR_COMFAST_CF_E530N) &&\
+ !defined(CONFIG_FOR_P2W_CPE505N) &&\
+ !defined(CONFIG_FOR_P2W_R602N) &&\
!defined(CONFIG_FOR_WALLYS_DR531) &&\
!defined(CONFIG_FOR_YUNCORE_AP90Q) &&\
!defined(CONFIG_FOR_YUNCORE_CPE830) &&\
#define CONFIG_UPG_UBOOT_SIZE_BACKUP_HEX 0x20000
#endif
-#if defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
+#if defined(CONFIG_FOR_P2W_CPE505N) ||\
+ defined(CONFIG_FOR_P2W_R602N) ||\
+ defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
defined(CONFIG_FOR_YUNCORE_CPE830) ||\
defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
#define CONFIG_UPG_SCRIPTS_FW_ADDR_HEX 0x9F050000