/*
- * This file contains the configuration parameters for the DB12x (AR9344) board.
+ * Copyright (C) 2016 Piotr Dymacz <piotr@dymacz.pl>
+ *
+ * This file contains the configuration parameters
+ * for Qualcomm Atheros QCA953x based devices
+ *
+ * Reference designs: AP143
+ *
+ * SPDX-License-Identifier: GPL-2.0
*/
-#ifndef _AP143_CONFIG_H
-#define _AP143_CONFIG_H
+#ifndef _AP143_H
+#define _AP143_H
#include <config.h>
-#include <atheros.h>
+#include <configs/qca9k_common.h>
+#include <soc/soc_common.h>
/*
- * FLASH and environment organization
+ * ==================
+ * GPIO configuration
+ * ==================
*/
-#define CFG_MAX_FLASH_BANKS 1
-#define CFG_MAX_FLASH_SECT 4096 // 4 KB sectors in 16 MB flash
-#define CFG_FLASH_SECTOR_SIZE 64 * 1024
-/*
- * We boot from this flash
- */
-#define CFG_FLASH_BASE 0x9F000000
-#ifdef COMPRESSED_UBOOT
- #define BOOTSTRAP_TEXT_BASE CFG_FLASH_BASE
- #define BOOTSTRAP_CFG_MONITOR_BASE BOOTSTRAP_TEXT_BASE
-#endif
+#if defined(CONFIG_FOR_COMFAST_CF_E314N)
+
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO4 | GPIO11 | GPIO14 |\
+ GPIO15 | GPIO16
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO0 | GPIO2 | GPIO3
+ #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_H |\
+ CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_IN GPIO17
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
+
+#elif defined(CONFIG_FOR_COMFAST_CF_E320N_V2)
+
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO0 | GPIO2 | GPIO3
+ #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_H
+ #define CONFIG_QCA_GPIO_MASK_IN GPIO11 | GPIO12 | GPIO14 |\
+ GPIO16 | GPIO17
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
+
+#elif defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E530N)
+
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO11
+ #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_IN GPIO17
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
+#elif defined(CONFIG_FOR_P2W_CPE505N)
+
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO4 | GPIO11 | GPIO12 |\
+ GPIO14 | GPIO15
+ #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_IN GPIO17
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
+#elif defined(CONFIG_FOR_P2W_R602N)
+
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO4 | GPIO11 | GPIO12 |\
+ GPIO14 | GPIO15 | GPIO16
+ #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_IN GPIO17
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
+#elif defined(CONFIG_FOR_TPLINK_WA850RE_V2)
+
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO0 | GPIO1 | GPIO2 |\
+ GPIO3 | GPIO4 | GPIO12 |\
+ GPIO13 | GPIO14
+ #define CONFIG_QCA_GPIO_MASK_OUT GPIO15 |\
+ CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_IN GPIO16 | GPIO17
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO15 |\
+ CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
+#elif defined(CONFIG_FOR_TPLINK_WR810N)
+
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO13
+ #define CONFIG_QCA_GPIO_MASK_OUT GPIO11 |\
+ CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_IN GPIO0 | GPIO1 | GPIO12
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO11 |\
+ CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
+#elif defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
+ defined(CONFIG_FOR_TPLINK_WR802N)
+
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO13
+ #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_IN GPIO12
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
+#elif defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V9)
+
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO3 | GPIO4 | GPIO11 |\
+ GPIO13 | GPIO14 | GPIO15 |\
+ GPIO16
+ #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_IN GPIO12 | GPIO17
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
+#elif defined(CONFIG_FOR_TPLINK_WR841N_V11)
+
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO1 | GPIO2 | GPIO3 |\
+ GPIO4 | GPIO11 | GPIO13 |\
+ GPIO14 | GPIO15 | GPIO16
+ #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_IN GPIO12 | GPIO17
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
+#elif defined(CONFIG_FOR_TPLINK_WR842N_V3)
+
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO2 | GPIO3 | GPIO4 |\
+ GPIO11 | GPIO12 | GPIO13 |\
+ GPIO14 | GPIO15 | GPIO16 |\
+ GPIO17
+ #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_IN GPIO0 | GPIO1
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
+#elif defined(CONFIG_FOR_TPLINK_WR902AC_V1)
+
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_H GPIO4 | GPIO13 | GPIO15
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO0 | GPIO11 | GPIO12
+ #define CONFIG_QCA_GPIO_MASK_OUT GPIO1 |\
+ CONFIG_QCA_GPIO_MASK_LED_ACT_H |\
+ CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_IN GPIO2 | GPIO3 | GPIO14 | GPIO17
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H GPIO1 |\
+ CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_L CONFIG_QCA_GPIO_MASK_LED_ACT_H
+
+#elif defined(CONFIG_FOR_WALLYS_DR531)
+
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO11 | GPIO12 | GPIO13 |\
+ GPIO14 | GPIO15 | GPIO16
+ #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_IN GPIO17
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
+#elif defined(CONFIG_FOR_YUNCORE_AP90Q)
+
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO4 | GPIO12 | GPIO16
+ #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_IN GPIO17
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
+#elif defined(CONFIG_FOR_YUNCORE_CPE830)
+
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO0 | GPIO1 | GPIO2 |\
+ GPIO3 | GPIO4 | GPIO12 |\
+ GPIO16
+ #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_IN GPIO17
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
+
+#elif defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
+
+ #define CONFIG_QCA_GPIO_MASK_LED_ACT_L GPIO4 | GPIO11 | GPIO12 |\
+ GPIO13 | GPIO14 | GPIO15 |\
+ GPIO16
+ #define CONFIG_QCA_GPIO_MASK_OUT CONFIG_QCA_GPIO_MASK_LED_ACT_L
+ #define CONFIG_QCA_GPIO_MASK_IN GPIO17
+ #define CONFIG_QCA_GPIO_MASK_OUT_INIT_H CONFIG_QCA_GPIO_MASK_LED_ACT_L
-/*
- * The following #defines are needed to get flash environment right
- */
-#define CFG_MONITOR_BASE TEXT_BASE
-#define CFG_MONITOR_LEN (192 << 10)
+#endif
/*
+ * ================
* Default bootargs
+ * ================
*/
-#undef CONFIG_BOOTARGS
-#if defined(CONFIG_FOR_TPLINK_WR820N_CH)
-#define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init mtdparts=mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(ART)"
-#endif
+#if defined(CONFIG_FOR_COMFAST_CF_E314N) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E320N_V2)
-/*
- * Other env default values
- */
-#undef CONFIG_BOOTFILE
-#define CONFIG_BOOTFILE "firmware.bin"
+ #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:03 "\
+ "rootfstype=jffs2 init=/sbin/init "\
+ "mtdparts=ath-nor0:64k(u-boot),64k(art),1536k(uImage),14656k(rootfs),64k(mib0)"
-#undef CONFIG_LOADADDR
-#define CONFIG_LOADADDR 0x80800000
+#elif defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E530N)
-#define CFG_LOAD_ADDR 0x9F020000
-#define UPDATE_SCRIPT_FW_ADDR "0x9F020000"
-#define CONFIG_BOOTCOMMAND "bootm 0x9F020000"
+ #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:03 "\
+ "rootfstype=jffs2 init=/sbin/init "\
+ "mtdparts=ath-nor0:64k(u-boot),64k(art),1536k(uImage),6464k(rootfs),64k(mib0)"
+#elif defined(CONFIG_FOR_P2W_CPE505N) ||\
+ defined(CONFIG_FOR_P2W_R602N) ||\
+ defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
+ defined(CONFIG_FOR_YUNCORE_CPE830) ||\
+ defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
-#define CONFIG_IPADDR 192.168.1.1
-#define CONFIG_SERVERIP 192.168.1.2
+ #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
+ "rootfstype=squashfs init=/sbin/init "\
+ "mtdparts=spi0.0:256k(u-boot),64k(u-boot-env),14528k(rootfs),1472k(kernel),64k(art),16000k(firmware)"
-#undef CFG_PLL_FREQ
-#undef CFG_HZ
+#elif defined(CONFIG_FOR_TPLINK_WR810N)
-// CPU-RAM-AHB frequency setting
-//#define CFG_PLL_FREQ CFG_PLL_650_400_200
-//#define CFG_PLL_FREQ 0x13
-#define CFG_HZ_FALLBACK (650000000LU/2)
+ #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
+ "rootfstype=squashfs init=/sbin/init "\
+ "mtdparts=ath-nor0:128k(u-boot),1024k(kernel),6912k(rootfs),64k(config),64k(art)"
-#define CFG_HZ bd->bi_cfg_hz
-#define AR7240_SPI_CONTROL 0x43
-#define AR7240_SPI_CONTROL_DEFAULT AR7240_SPI_CONTROL
-/*
- * MIPS32 24K Processor Core Family Software User's Manual
- *
- * 6.2.9 Count Register (CP0 Register 9, Select 0)
- * The Count register acts as a timer, incrementing at a constant
- * rate, whether or not an instruction is executed, retired, or
- * any forward progress is made through the pipeline. The counter
- * increments every other clock, if the DC bit in the Cause register
- * is 0.
- *
- * Since the count is incremented every other tick, divide by 2
- * XXX derive this from CFG_PLL_FREQ
- */
+#elif defined(CONFIG_FOR_TPLINK_WR820N_CN)
+ #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
+ "rootfstype=squashfs init=/sbin/init "\
+ "mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(art)"
+#elif defined(CONFIG_FOR_TPLINK_WA850RE_V2) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V11) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\
+ defined(CONFIG_FOR_TPLINK_WR802N)
-/*
- * Address and size of Primary Environment Sector
- */
-#define CFG_ENV_IS_IN_FLASH 1
-#undef CFG_ENV_IS_NOWHERE
+ #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
+ "rootfstype=squashfs init=/sbin/init "\
+ "mtdparts=ath-nor0:128k(u-boot),1024k(kernel),2816k(rootfs),64k(config),64k(art)"
-#define CFG_ENV_ADDR 0x9F01EC00
-#define CFG_ENV_SIZE 0x1000
-#define CFG_ENV_SECT_SIZE 0x10000
-
-/*
- * Available commands
- */
-#define CONFIG_COMMANDS (CFG_CMD_MEMORY | \
- CFG_CMD_DHCP | \
- CFG_CMD_PING | \
- CFG_CMD_FLASH | \
- CFG_CMD_NET | \
- CFG_CMD_RUN | \
- CFG_CMD_DATE | \
- CFG_CMD_SNTP | \
- CFG_CMD_ECHO | \
- CFG_CMD_BOOTD | \
- CFG_CMD_ITEST | \
- CFG_CMD_ENV | \
- CFG_CMD_LOADB)
+#elif defined(CONFIG_FOR_TPLINK_WR842N_V3) ||\
+ defined(CONFIG_FOR_TPLINK_WR902AC_V1)
-// Enable NetConsole and custom NetConsole port
-#define CONFIG_NETCONSOLE
-#define CONFIG_NETCONSOLE_PORT 6666
+ #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
+ "rootfstype=jffs2 init=/sbin/init "\
+ "mtdparts=ath-nor0:32k(u-boot1),32k(u-boot2),3008k(rootfs),896k(uImage),64k(mib0),64k(ART)"
+#elif defined(CONFIG_FOR_WALLYS_DR531)
+ #define CONFIG_BOOTARGS "console=ttyS0,115200 root=31:02 "\
+ "rootfstype=jffs2 init=/sbin/init "\
+ "mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),64k(mib0),64k(ART)"
+#endif
+/*
+ * =============================
+ * Load address and boot command
+ * =============================
+ */
+#if defined(CONFIG_FOR_COMFAST_CF_E314N) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E530N) ||\
+ defined(CONFIG_FOR_TPLINK_WA850RE_V2) ||\
+ defined(CONFIG_FOR_TPLINK_WR802N) ||\
+ defined(CONFIG_FOR_TPLINK_WR810N) ||\
+ defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V11) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\
+ defined(CONFIG_FOR_TPLINK_WR842N_V3) ||\
+ defined(CONFIG_FOR_TPLINK_WR902AC_V1)
+ #define CFG_LOAD_ADDR 0x9F020000
+#elif defined(CONFIG_FOR_P2W_CPE505N) ||\
+ defined(CONFIG_FOR_P2W_R602N) ||\
+ defined(CONFIG_FOR_WALLYS_DR531) ||\
+ defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
+ defined(CONFIG_FOR_YUNCORE_CPE830) ||\
+ defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
+ #define CFG_LOAD_ADDR 0x9F050000
+#endif
+#if defined(CONFIG_FOR_P2W_CPE505N) ||\
+ defined(CONFIG_FOR_P2W_R602N) ||\
+ defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
+ defined(CONFIG_FOR_YUNCORE_CPE830) ||\
+ defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
+ #define CONFIG_BOOTCOMMAND "bootm 0x9F050000 || bootm 0x9FE80000"
+#else
+ #define CONFIG_BOOTCOMMAND "bootm " MK_STR(CFG_LOAD_ADDR)
+#endif
+/*
+ * =========================
+ * Environment configuration
+ * =========================
+ */
+#if defined(CONFIG_FOR_COMFAST_CF_E314N) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E530N)
+ #define CFG_ENV_ADDR 0x9F018000
+ #define CFG_ENV_SIZE 0x7C00
+ #define CFG_ENV_SECT_SIZE 0x10000
+#elif defined(CONFIG_FOR_P2W_CPE505N) ||\
+ defined(CONFIG_FOR_P2W_R602N) ||\
+ defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
+ defined(CONFIG_FOR_YUNCORE_CPE830) ||\
+ defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
+ #define CFG_ENV_ADDR 0x9F040000
+ #define CFG_ENV_SIZE 0xFC00
+ #define CFG_ENV_SECT_SIZE 0x10000
+#elif defined(CONFIG_FOR_TPLINK_WA850RE_V2) ||\
+ defined(CONFIG_FOR_TPLINK_WR802N) ||\
+ defined(CONFIG_FOR_TPLINK_WR810N) ||\
+ defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V11) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\
+ defined(CONFIG_FOR_TPLINK_WR842N_V3) ||\
+ defined(CONFIG_FOR_TPLINK_WR902AC_V1)
+ #define CFG_ENV_ADDR 0x9F01EC00
+ #define CFG_ENV_SIZE 0x1000
+ #define CFG_ENV_SECT_SIZE 0x10000
+#elif defined(CONFIG_FOR_WALLYS_DR531)
+ #define CFG_ENV_ADDR 0x9F030000
+ #define CFG_ENV_SIZE 0xF800
+ #define CFG_ENV_SECT_SIZE 0x10000
+#endif
-/*modify from 0x4138 to 0x40c3, ddr refresh interval: 12uS to 7.8uS. by wkp
- from Li Guanwen, 30Dec14. */
-//#define CFG_DDR_REFRESH_VAL 0x40c3 (??????????????????)
-#define CFG_DDR_REFRESH_VAL 0x4138
-
-
-
-
-
+/*
+ * ===========================
+ * List of available baudrates
+ * ===========================
+ */
+#define CFG_BAUDRATE_TABLE \
+ { 600, 1200, 2400, 4800, 9600, 14400, \
+ 19200, 28800, 38400, 56000, 57600, 115200 }
/*
- * Web Failsafe configuration
+ * ==================================================
+ * MAC address/es, model and WPS pin offsets in FLASH
+ * ==================================================
*/
-#define WEBFAILSAFE_UPLOAD_RAM_ADDRESS CONFIG_LOADADDR
-#define WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS CFG_FLASH_BASE
+#if defined(CONFIG_FOR_COMFAST_CF_E314N) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E530N)
+ #define OFFSET_MAC_DATA_BLOCK 0x10000
+ #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x10000
+ #define OFFSET_MAC_ADDRESS 0x00000
+#elif defined(CONFIG_FOR_P2W_CPE505N) ||\
+ defined(CONFIG_FOR_P2W_R602N) ||\
+ defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
+ defined(CONFIG_FOR_YUNCORE_CPE830) ||\
+ defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
+ #define OFFSET_MAC_DATA_BLOCK 0xFF0000
+ #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
+ #define OFFSET_MAC_ADDRESS 0x000000
+#elif defined(CONFIG_FOR_TPLINK_WA850RE_V2)
+ #define OFFSET_MAC_DATA_BLOCK 0x3c0000
+ #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
+ #define OFFSET_MAC_ADDRESS 0x000008
+#elif defined(CONFIG_FOR_TPLINK_WR802N) ||\
+ defined(CONFIG_FOR_TPLINK_WR810N) ||\
+ defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V11) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\
+ defined(CONFIG_FOR_TPLINK_WR842N_V3)
+ #define OFFSET_MAC_DATA_BLOCK 0x010000
+ #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
+ #define OFFSET_MAC_ADDRESS 0x00FC00
+ #define OFFSET_ROUTER_MODEL 0x00FD00
+ #define OFFSET_PIN_NUMBER 0x00FE00
+#elif defined(CONFIG_FOR_TPLINK_WR902AC_V1)
+ #define OFFSET_MAC_DATA_BLOCK 0x750000
+ #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
+ #define OFFSET_MAC_ADDRESS 0x000008
+#elif defined(CONFIG_FOR_WALLYS_DR531)
+ #define OFFSET_MAC_DATA_BLOCK 0x030000
+ #define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
+ #define OFFSET_MAC_ADDRESS 0x00F810
+#endif
-// Firmware partition offset
-#define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS WEBFAILSAFE_UPLOAD_UBOOT_ADDRESS + 0x20000
+/*
+ * =========================
+ * Custom changes per device
+ * =========================
+ */
-// U-Boot partition size
-#define WEBFAILSAFE_UPLOAD_UBOOT_SIZE_IN_BYTES (CONFIG_MAX_UBOOT_SIZE_KB * 1024)
+/*
+ * Comfast CF-E520N and E320Nv2 are limited to 64 KB only,
+ * disable some commands
+ */
+#if defined(CONFIG_FOR_COMFAST_CF_E314N) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E530N)
+ #undef CONFIG_CMD_DHCP
+ #undef CONFIG_CMD_LOADB
+ #undef CONFIG_CMD_SNTP
+ #undef CONFIG_UPG_SCRIPTS_UBOOT
+#endif
-// TODO: should be == CONFIG_MAX_UBOOT_SIZE_KB
-#define UPDATE_SCRIPT_UBOOT_SIZE_IN_BYTES "0x1EC00"
-#define UPDATE_SCRIPT_UBOOT_BACKUP_SIZE_IN_BYTES "0x20000"
+/*
+ * ===========================
+ * HTTP recovery configuration
+ * ===========================
+ */
+#define WEBFAILSAFE_UPLOAD_KERNEL_ADDRESS CFG_LOAD_ADDR
-// ART partition size
-#define WEBFAILSAFE_UPLOAD_ART_SIZE_IN_BYTES (64 * 1024)
+#if defined(CONFIG_FOR_COMFAST_CF_E314N) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E530N)
+ #define WEBFAILSAFE_UPLOAD_ART_ADDRESS (CFG_FLASH_BASE + 0x10000)
+#endif
-// max. firmware size <= (FLASH_SIZE - WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES)
-// TP-Link: 64k(U-Boot),64k(MAC/model/WPS pin block),64k(ART)
-#define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024)
+/* Firmware size limit */
+#if defined(CONFIG_FOR_COMFAST_CF_E314N) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E530N) ||\
+ defined(CONFIG_FOR_TPLINK_WR802N) ||\
+ defined(CONFIG_FOR_TPLINK_WR810N) ||\
+ defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V11) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\
+ defined(CONFIG_FOR_TPLINK_WR842N_V3)
+ #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (192 * 1024)
+#elif defined(CONFIG_FOR_TPLINK_WA850RE_V2)
+ #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (448 * 1024)
+#elif defined(CONFIG_FOR_TPLINK_WR902AC_V1)
+ #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (832 * 1024)
+#elif defined(CONFIG_FOR_P2W_CPE505N) ||\
+ defined(CONFIG_FOR_P2W_R602N) ||\
+ defined(CONFIG_FOR_WALLYS_DR531) ||\
+ defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
+ defined(CONFIG_FOR_YUNCORE_CPE830) ||\
+ defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
+ #define WEBFAILSAFE_UPLOAD_LIMITED_AREA_IN_BYTES (384 * 1024)
+#endif
-// progress state info
-#define WEBFAILSAFE_PROGRESS_START 0
-#define WEBFAILSAFE_PROGRESS_TIMEOUT 1
-#define WEBFAILSAFE_PROGRESS_UPLOAD_READY 2
-#define WEBFAILSAFE_PROGRESS_UPGRADE_READY 3
-#define WEBFAILSAFE_PROGRESS_UPGRADE_FAILED 4
+/*
+ * ========================
+ * PLL/Clocks configuration
+ * ========================
+ */
+#if defined(CONFIG_FOR_TPLINK_WA850RE_V2) ||\
+ defined(CONFIG_FOR_TPLINK_WR802N) ||\
+ defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V9)
+ #define CONFIG_QCA_PLL QCA_PLL_PRESET_550_400_200
+#else
+ #define CONFIG_QCA_PLL QCA_PLL_PRESET_650_400_200
+#endif
-// update type
-#define WEBFAILSAFE_UPGRADE_TYPE_FIRMWARE 0
-#define WEBFAILSAFE_UPGRADE_TYPE_UBOOT 1
-#define WEBFAILSAFE_UPGRADE_TYPE_ART 2
+#if defined(CONFIG_FOR_COMFAST_CF_E314N) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E320N_V2) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E520N) ||\
+ defined(CONFIG_FOR_COMFAST_CF_E530N) ||\
+ defined(CONFIG_FOR_TPLINK_WA850RE_V2) ||\
+ defined(CONFIG_FOR_TPLINK_WR802N) ||\
+ defined(CONFIG_FOR_TPLINK_WR810N) ||\
+ defined(CONFIG_FOR_TPLINK_WR820N_CN) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V10) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V11) ||\
+ defined(CONFIG_FOR_TPLINK_WR841N_V9) ||\
+ defined(CONFIG_FOR_TPLINK_WR842N_V3) ||\
+ defined(CONFIG_FOR_TPLINK_WR902AC_V1)
+
+ #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x10000
+ #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000
+
+#elif defined(CONFIG_FOR_P2W_CPE505N) ||\
+ defined(CONFIG_FOR_P2W_R602N) ||\
+ defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
+ defined(CONFIG_FOR_YUNCORE_CPE830) ||\
+ defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
+
+ #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x40000
+ #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000
+
+#elif defined(CONFIG_FOR_WALLYS_DR531)
+
+ #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_OFFSET 0x30000
+ #define CONFIG_QCA_PLL_IN_FLASH_BLOCK_SIZE 0x10000
-/*-----------------------------------------------------------------------*/
+#endif
/*
- * Additional environment variables for simple upgrades
+ * ==================================
+ * For upgrade scripts in environment
+ * ==================================
*/
-//#define CONFIG_EXTRA_ENV_SETTINGS SILENT_ENV_VARIABLE
+#if !defined(CONFIG_FOR_COMFAST_CF_E314N) &&\
+ !defined(CONFIG_FOR_COMFAST_CF_E320N_V2) &&\
+ !defined(CONFIG_FOR_COMFAST_CF_E520N) &&\
+ !defined(CONFIG_FOR_COMFAST_CF_E530N) &&\
+ !defined(CONFIG_FOR_P2W_CPE505N) &&\
+ !defined(CONFIG_FOR_P2W_R602N) &&\
+ !defined(CONFIG_FOR_WALLYS_DR531) &&\
+ !defined(CONFIG_FOR_YUNCORE_AP90Q) &&\
+ !defined(CONFIG_FOR_YUNCORE_CPE830) &&\
+ !defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
+ #define CONFIG_UPG_UBOOT_SIZE_BACKUP_HEX 0x20000
+#endif
+
+#if defined(CONFIG_FOR_P2W_CPE505N) ||\
+ defined(CONFIG_FOR_P2W_R602N) ||\
+ defined(CONFIG_FOR_YUNCORE_AP90Q) ||\
+ defined(CONFIG_FOR_YUNCORE_CPE830) ||\
+ defined(CONFIG_FOR_ZBTLINK_ZBT_WE1526)
+ #define CONFIG_UPG_SCRIPTS_FW_ADDR_HEX 0x9F050000
+#endif
/*
- * Cache lock for stack
+ * ===================
+ * Other configuration
+ * ===================
*/
-#define CFG_INIT_SP_OFFSET 0x1000
+
+/* Cache lock for stack */
#define CONFIG_INIT_SRAM_SP_OFFSET 0xbd001800
-/* For Merlin, both PCI, PCI-E interfaces are valid */
-#define ATH_ART_PCICFG_OFFSET 12
-/* use eth1(LAN) as the net interface */
-#define CONFIG_AG7240_SPEPHY
-#define CONFIG_NET_MULTI
-#define CONFIG_PCI 1
-#define WLANCAL 0x9fff1000
-#define BOARDCAL 0x9fff0000
-#define CFG_MII0_RMII 1
-#define CFG_BOOTM_LEN (16 << 20) /* 16 MB */
-
-#undef DEBUG
-
-/* MAC address, model and PIN number offsets in FLASH */
-#define OFFSET_MAC_DATA_BLOCK 0x010000
-#define OFFSET_MAC_DATA_BLOCK_LENGTH 0x010000
-#define OFFSET_MAC_ADDRESS 0x00FC00
-#define OFFSET_ROUTER_MODEL 0x00FD00
-#define OFFSET_PIN_NUMBER 0x00FE00
-
-#include <cmd_confdefs.h>
-
-#endif /* __AP143_CONFIG_H */
+#endif /* _AP143_H */
projects / oweals / u-boot_mod.git / blobdiff