// WASP BootStrap Register
#define WASP_BOOTSTRAP_REG (AR7240_RESET_BASE + 0xb0)
+#define WASP_BOOTSTRAP_SDRAM_DISABLE_SHIFT 1
+#define WASP_BOOTSTRAP_SDRAM_DISABLE_MASK (1 << WASP_BOOTSTRAP_SDRAM_DISABLE_SHIFT)
+#define WASP_BOOTSTRAP_DDR_SELECT_SHIFT 0
+#define WASP_BOOTSTRAP_DDR_SELECT_MASK (1 << WASP_BOOTSTRAP_DDR_SELECT_SHIFT)
+#define WASP_BOOTSTRAP_DDR_WIDTH_SHIFT 21
+#define WASP_BOOTSTRAP_DDR_WIDTH_MASK (1 << WASP_BOOTSTRAP_DDR_WIDTH_SHIFT)
#define WASP_REF_CLK_25 (1 << 4) /* 0 - 25MHz 1 - 40 MHz */
#define WASP_RAM_TYPE(a) ((a) & 0x3)
#define CFG_934X_DDR1_CONFIG_VAL 0x7fd48cd0 // 0xc7d48cd0
#define CFG_934X_DDR1_MODE_VAL_INIT 0x133
-#define CFG_934X_DDR1_EXT_MODE_VAL 0x2 // 0x0
+#define CFG_934X_DDR1_EXT_MODE_VAL 0x0
#define CFG_934X_DDR1_MODE_VAL 0x33
#define CFG_934X_DDR1_CONFIG2_VAL 0x99d0e6a8 // 0x9dd0e6a8