+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2009
* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
* (C) Copyright 2008
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
#include "imagetool.h"
#include <image.h>
#include "imximage.h"
+#include <generated/autoconf.h>
#define UNDEFINED 0xFFFFFFFF
+#if !defined(CONFIG_IMX_DCD_ADDR)
+#define CONFIG_IMX_DCD_ADDR 0x00910000
+#endif
/*
* Supported commands for configuration file
*/
{CMD_BOOT_OFFSET, "BOOT_OFFSET", "Boot offset", },
{CMD_WRITE_DATA, "DATA", "Reg Write Data", },
{CMD_WRITE_CLR_BIT, "CLR_BIT", "Reg clear bit", },
+ {CMD_WRITE_SET_BIT, "SET_BIT", "Reg set bit", },
{CMD_CHECK_BITS_SET, "CHECK_BITS_SET", "Reg Check bits set", },
{CMD_CHECK_BITS_CLR, "CHECK_BITS_CLR", "Reg Check bits clr", },
{CMD_CSF, "CSF", "Command Sequence File", },
d->write_dcd_command.length = cpu_to_be16(4);
d->write_dcd_command.param = DCD_WRITE_CLR_BIT_PARAM;
break;
+ case CMD_WRITE_SET_BIT:
+ if ((d->write_dcd_command.tag == DCD_WRITE_DATA_COMMAND_TAG) &&
+ (d->write_dcd_command.param == DCD_WRITE_SET_BIT_PARAM))
+ break;
+ d = d2;
+ d->write_dcd_command.tag = DCD_WRITE_DATA_COMMAND_TAG;
+ d->write_dcd_command.length = cpu_to_be16(4);
+ d->write_dcd_command.param = DCD_WRITE_SET_BIT_PARAM;
+ break;
/*
* Check data command only supports one entry,
*/
genimg_print_size(hdr_v2->boot_data.size);
printf("Load Address: %08x\n", (uint32_t)fhdr_v2->boot_data_ptr);
printf("Entry Point: %08x\n", (uint32_t)fhdr_v2->entry);
- if (fhdr_v2->csf && (imximage_ivt_offset != UNDEFINED) &&
- (imximage_csf_size != UNDEFINED)) {
+ if (fhdr_v2->csf) {
uint16_t dcdlen;
int offs;
offs = (char *)&hdr_v2->data.dcd_table
- (char *)hdr_v2;
- printf("HAB Blocks: %08x %08x %08x\n",
+ /*
+ * The HAB block is the first part of the image, from
+ * start of IVT header (fhdr_v2->self) to the start of
+ * the CSF block (fhdr_v2->csf). So HAB size is
+ * calculated as:
+ * HAB_size = fhdr_v2->csf - fhdr_v2->self
+ */
+ printf("HAB Blocks: 0x%08x 0x%08x 0x%08x\n",
(uint32_t)fhdr_v2->self, 0,
- hdr_v2->boot_data.size - imximage_ivt_offset -
- imximage_csf_size);
- printf("DCD Blocks: 00910000 %08x %08x\n",
- offs, be16_to_cpu(dcdlen));
+ (uint32_t)(fhdr_v2->csf - fhdr_v2->self));
+ printf("DCD Blocks: 0x%08x 0x%08x 0x%08x\n",
+ offs, CONFIG_IMX_DCD_ADDR, be16_to_cpu(dcdlen));
}
} else {
imx_header_v2_t *next_hdr_v2;
break;
case CMD_WRITE_DATA:
case CMD_WRITE_CLR_BIT:
+ case CMD_WRITE_SET_BIT:
case CMD_CHECK_BITS_SET:
case CMD_CHECK_BITS_CLR:
value = get_cfg_value(token, name, lineno);
switch(*cmd) {
case CMD_WRITE_DATA:
case CMD_WRITE_CLR_BIT:
+ case CMD_WRITE_SET_BIT:
case CMD_CHECK_BITS_SET:
case CMD_CHECK_BITS_CLR: