misc: fs_loader: Use device_get_global_by_ofnode to get to node

[oweals/u-boot.git] / test / dm / pmic.c

diff --git a/test/dm/pmic.c b/test/dm/pmic.c
index e9c904c9f15f842eaf9c0cf80b39fa2072c9fd28..b582329a9c599b9d302244ec1dd7fb78d409de8f 100644 (file)
--- a/test/dm/pmic.c
+++ b/test/dm/pmic.c
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Tests for the driver model pmic API
  *
  * Copyright (c) 2015 Samsung Electronics
  * Przemyslaw Marczak <p.marczak@samsung.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -14,19 +13,18 @@
 #include <malloc.h>
 #include <dm/device-internal.h>
 #include <dm/root.h>
-#include <dm/ut.h>
 #include <dm/util.h>
 #include <dm/test.h>
 #include <dm/uclass-internal.h>
 #include <power/pmic.h>
 #include <power/sandbox_pmic.h>
-
-DECLARE_GLOBAL_DATA_PTR;
+#include <test/ut.h>
+#include <fsl_pmic.h>
 
 /* Test PMIC get method */
-static int dm_test_power_pmic_get(struct dm_test_state *dms)
+
+static inline int power_pmic_get(struct unit_test_state *uts, char *name)
 {
-       const char *name = "sandbox_pmic";
        struct udevice *dev;
 
        ut_assertok(pmic_get(name, &dev));
@@ -37,10 +35,28 @@ static int dm_test_power_pmic_get(struct dm_test_state *dms)
 
        return 0;
 }
+
+/* Test PMIC get method */
+static int dm_test_power_pmic_get(struct unit_test_state *uts)
+{
+       power_pmic_get(uts, "sandbox_pmic");
+
+       return 0;
+}
 DM_TEST(dm_test_power_pmic_get, DM_TESTF_SCAN_FDT);
 
+/* PMIC get method - MC34708 - for 3 bytes transmission */
+static int dm_test_power_pmic_mc34708_get(struct unit_test_state *uts)
+{
+       power_pmic_get(uts, "pmic@41");
+
+       return 0;
+}
+
+DM_TEST(dm_test_power_pmic_mc34708_get, DM_TESTF_SCAN_FDT);
+
 /* Test PMIC I/O */
-static int dm_test_power_pmic_io(struct dm_test_state *dms)
+static int dm_test_power_pmic_io(struct unit_test_state *uts)
 {
        const char *name = "sandbox_pmic";
        uint8_t out_buffer, in_buffer;
@@ -67,3 +83,48 @@ static int dm_test_power_pmic_io(struct dm_test_state *dms)
        return 0;
 }
 DM_TEST(dm_test_power_pmic_io, DM_TESTF_SCAN_FDT);
+
+#define MC34708_PMIC_REG_COUNT 64
+#define MC34708_PMIC_TEST_VAL 0x125534
+static int dm_test_power_pmic_mc34708_regs_check(struct unit_test_state *uts)
+{
+       struct udevice *dev;
+       int reg_count;
+
+       ut_assertok(pmic_get("pmic@41", &dev));
+
+       /* Check number of PMIC registers */
+       reg_count = pmic_reg_count(dev);
+       ut_asserteq(reg_count, MC34708_PMIC_REG_COUNT);
+
+       return 0;
+}
+
+DM_TEST(dm_test_power_pmic_mc34708_regs_check, DM_TESTF_SCAN_FDT);
+
+static int dm_test_power_pmic_mc34708_rw_val(struct unit_test_state *uts)
+{
+       struct udevice *dev;
+       int val;
+
+       ut_assertok(pmic_get("pmic@41", &dev));
+
+       /* Check if single 3 byte read is successful */
+       val = pmic_reg_read(dev, REG_POWER_CTL2);
+       ut_asserteq(val, 0x422100);
+
+       /* Check if RW works */
+       val = 0;
+       ut_assertok(pmic_reg_write(dev, REG_RTC_TIME, val));
+       ut_assertok(pmic_reg_write(dev, REG_RTC_TIME, MC34708_PMIC_TEST_VAL));
+       val = pmic_reg_read(dev, REG_RTC_TIME);
+       ut_asserteq(val, MC34708_PMIC_TEST_VAL);
+
+       pmic_clrsetbits(dev, REG_POWER_CTL2, 0x3 << 8, 1 << 9);
+       val = pmic_reg_read(dev, REG_POWER_CTL2);
+       ut_asserteq(val, (0x422100 & ~(0x3 << 8)) | (1 << 9));
+
+       return 0;
+}
+
+DM_TEST(dm_test_power_pmic_mc34708_rw_val, DM_TESTF_SCAN_FDT);