ramips: make rt2880_pci_base static

[oweals/openwrt.git] / target / linux / ramips / files / arch / mips / pci / pci-rt288x.c

diff --git a/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c b/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c
index e29741901232425d11e469c4ad6a285faf369463..fb3a6b13e5ccee1ce630efaba9a5542adb02aef5 100644 (file)
--- a/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c
+++ b/target/linux/ramips/files/arch/mips/pci/pci-rt288x.c
@@ -1,3 +1,16 @@
+/*
+ *  Ralink RT288x SoC PCI register definitions
+ *
+ *  Copyright (C) 2009 John Crispin <blogic@openwrt.org>
+ *  Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
+ *
+ *  Parts of this file are based on Ralink's 2.6.21 BSP
+ *
+ *  This program is free software; you can redistribute it and/or modify it
+ *  under the terms of the GNU General Public License version 2 as published
+ *  by the Free Software Foundation.
+ */
+
 #include <linux/types.h>
 #include <linux/pci.h>
 #include <linux/io.h>
@@ -6,7 +19,10 @@
 #include <asm/mach-ralink/rt288x.h>
 #include <asm/mach-ralink/rt288x_regs.h>
 
-#define RT2880_PCI_SLOT1_BASE          0x20000000
+#define RT2880_PCI_MEM_BASE    0x20000000
+#define RT2880_PCI_MEM_SIZE    0x10000000
+#define RT2880_PCI_IO_BASE     0x00460000
+#define RT2880_PCI_IO_SIZE     0x00010000
 
 #define RT2880_PCI_REG_PCICFG_ADDR     0x00
 #define RT2880_PCI_REG_PCIMSK_ADDR     0x0c
@@ -24,7 +40,7 @@
 #define PCI_ACCESS_READ  0
 #define PCI_ACCESS_WRITE 1
 
-void __iomem *rt2880_pci_base;
+static void __iomem *rt2880_pci_base;
 
 static u32 rt2880_pci_reg_read(u32 reg)
 {
@@ -99,15 +115,15 @@ static struct pci_ops rt2880_pci_ops = {
 
 static struct resource rt2880_pci_io_resource = {
        .name   = "PCI MEM space",
-       .start  = 0x20000000,
-       .end    = 0x2FFFFFFF,
+       .start  = RT2880_PCI_MEM_BASE,
+       .end    = RT2880_PCI_MEM_BASE + RT2880_PCI_MEM_SIZE - 1,
        .flags  = IORESOURCE_MEM,
 };
 
 static struct resource rt2880_pci_mem_resource = {
        .name   = "PCI IO space",
-       .start  = 0x00460000,
-       .end    = 0x0046FFFF,
+       .start  = RT2880_PCI_IO_BASE,
+       .end    = RT2880_PCI_IO_BASE + RT2880_PCI_IO_SIZE - 1,
        .flags  = IORESOURCE_IO,
 };
 
@@ -117,9 +133,9 @@ static struct pci_controller rt2880_pci_controller = {
        .io_resource    = &rt2880_pci_mem_resource,
 };
 
-void inline read_config(unsigned long bus, unsigned long dev,
-                       unsigned long func, unsigned long reg,
-                       unsigned long *val)
+static inline void read_config(unsigned long bus, unsigned long dev,
+                              unsigned long func, unsigned long reg,
+                              unsigned long *val)
 {
        unsigned long address;
 
@@ -129,9 +145,9 @@ void inline read_config(unsigned long bus, unsigned long dev,
        *val = rt2880_pci_reg_read(RT2880_PCI_REG_CONFIG_DATA);
 }
 
-void inline write_config(unsigned long bus, unsigned long dev,
-                        unsigned long func, unsigned long reg,
-                        unsigned long val)
+static inline void write_config(unsigned long bus, unsigned long dev,
+                               unsigned long func, unsigned long reg,
+                               unsigned long val)
 {
        unsigned long address;
 
@@ -189,8 +205,8 @@ static int __init rt2880_pci_init(void)
 
        rt2880_pci_reg_write(0x79, RT2880_PCI_REG_ARBCTL);
        rt2880_pci_reg_write(0x07FF0001, RT2880_PCI_REG_BAR0SETUP_ADDR);
-       rt2880_pci_reg_write(RT2880_PCI_SLOT1_BASE, RT2880_PCI_REG_MEMBASE);
-       rt2880_pci_reg_write(0x00460000, RT2880_PCI_REG_IOBASE);
+       rt2880_pci_reg_write(RT2880_PCI_MEM_BASE, RT2880_PCI_REG_MEMBASE);
+       rt2880_pci_reg_write(RT2880_PCI_IO_BASE, RT2880_PCI_REG_IOBASE);
        rt2880_pci_reg_write(0x08000000, RT2880_PCI_REG_IMBASEBAR0_ADDR);
        rt2880_pci_reg_write(0x08021814, RT2880_PCI_REG_ID);
        rt2880_pci_reg_write(0x00800001, RT2880_PCI_REG_CLASS);