memory@0 {
reg = <0x0 0x4000000>;
};
-
- fpi@10000000 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "lantiq,fpi", "simple-bus";
- ranges = <0x0 0x10000000 0xEEFFFFF>;
- reg = <0x10000000 0xEF00000>;
+ cputemp@0 {
+ compatible = "lantiq,cputemp";
+ };
+
+ fpi@10000000 {
localbus@0 {
- #address-cells = <2>;
- #size-cells = <1>;
- compatible = "lantiq,localbus", "simple-bus";
+ nor-boot@0 {
+ compatible = "lantiq,nor";
+ bank-width = <2>;
+ reg = <0 0x0 0x800000>, <1 0x800000 0x800000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ boardconfig: partition@40000 {
+ label = "board_config";
+ reg = <0x40000 0x10000>;
+ read-only;
+ };
+ };
+ };
};
gpio: pinmux@E100B10 {
- compatible = "lantiq,pinctrl-xr9";
pinctrl-names = "default";
pinctrl-0 = <&state_default>;
- interrupt-parent = <&icu0>;
- interrupts = <166 135 66 40 41 42 38>;
-
- #gpio-cells = <2>;
- gpio-controller;
- reg = <0xE100B10 0xA0>;
-
state_default: pinmux {
stp {
lantiq,groups = "stp";
lantiq,function = "stp";
- };
- spi {
- lantiq,groups = "spi_di", "spi_do", "spi_clk";
- lantiq,function = "spi";
+ lantiq,open-drain = <0>;
+ lantiq,output = <1>;
+ lantiq,pull = <0>;
};
mdio {
lantiq,groups = "mdio";
lantiq,function = "mdio";
};
- gphy-leds_out {
- lantiq,pins = "io7", "io44";
- lantiq,pull = <0>;
- lantiq,output = <1>;
- };
- stp_out {
- lantiq,pins = "io4", "io5", "io6";
- lantiq,open-drain = <0>;
- lantiq,output = <1>;
- lantiq,pull = <0>;
- };
pci-rst {
lantiq,pins = "io21";
lantiq,open-drain = <0>;
lantiq,portmask = <0x3>;
};
+ ifxhcd@E106000 {
+ status = "okay";
+ gpios = <&gpio 32 0>;
+ };
+
pci@E105400 {
status = "okay";
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- compatible = "lantiq,pci-xway";
- bus-range = <0x0 0x0>;
- ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
- 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */
- reg = <0x7000000 0x8000 /* config space */
- 0xE105400 0x400>; /* pci bridge */
lantiq,bus-clock = <33333333>;
- /*lantiq,external-clock;*/
- lantiq,delay-hi = <0>; /* 0ns delay */
- lantiq,delay-lo = <0>; /* 0.0ns delay */
interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
interrupt-map = <
0x7000 0 0 1 &icu0 30 1 // slot 14, irq 30
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
- mac-address = [ 00 11 22 33 44 55 ];
+ mtd-mac-address = <&boardconfig 0x16>;
+ lantiq,switch;
ethernet@0 {
compatible = "lantiq,xrx200-pdi-port";
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
- mac-address = [ 00 11 22 33 44 56 ];
+ mtd-mac-address = <&boardconfig 0x16>;
+ mtd-mac-address-increment = <2>;
lantiq,wan;
+
ethernet@5 {
compatible = "lantiq,xrx200-pdi-port";
reg = <5>;
phy0: ethernet-phy@0 {
reg = <0x0>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
- lantiq,c45-reg-init = <1 0 0 0>;
};
phy1: ethernet-phy@1 {
reg = <0x1>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
- lantiq,c45-reg-init = <1 0 0 0>;
};
phy5: ethernet-phy@5 {
reg = <0x5>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
- lantiq,c45-reg-init = <1 0 0 0>;
};
phy11: ethernet-phy@11 {
reg = <0x11>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
- lantiq,c45-reg-init = <1 0 0 0>;
};
phy13: ethernet-phy@13 {
reg = <0x13>;
compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
- lantiq,c45-reg-init = <1 0 0 0>;
};
};
};